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4.4.
RAM ______________________________________________________________ 4-3
4.5.
Peripheral Circuit Control Registers _____________________________________ 4-4
4.5.1.
System-Protect Function _________________________________________________ 4-4
4.6.
Instruction Cache ___________________________________________________ 4-4
4.7.
Memory Mapped Access Area For External Flash Memory __________________ 4-4
4.8.
Control Registers ____________________________________________________ 4-5
5.
Interrupt ________________________________________________________ 5-1
5.1.
Overview __________________________________________________________ 5-1
5.2.
Vector Table ________________________________________________________ 5-2
5.2.1.
Vector Table Offset Address (VTOR) _________________________________________ 5-5
5.2.2.
Priority of Interrupts _____________________________________________________ 5-5
5.3.
Peripheral Circuit Interrupt Control _____________________________________ 5-5
5.4.
NMI ______________________________________________________________ 5-5
6.
DMA Controller (DMAC) ____________________________________________ 6-1
6.1.
Overview __________________________________________________________ 6-1
6.2.
Operations_________________________________________________________ 6-2
6.2.1.
Initialization ____________________________________________________________ 6-2
6.3.
Priority ____________________________________________________________ 6-2
6.4.
Data Structure ______________________________________________________ 6-2
6.4.1.
Transfer Source End Pointer _______________________________________________ 6-4
6.4.2.
Transfer Destination End Pointer ___________________________________________ 6-4
6.4.3.
Control Data ___________________________________________________________ 6-4
6.5.
DMA Transfer Mode _________________________________________________ 6-6
6.5.1.
Basic Transfer __________________________________________________________ 6-6
6.5.2.
Auto-Request Transfer ___________________________________________________ 6-6
6.5.3.
Ping-Pong Transfer ______________________________________________________ 6-7
6.5.4.
Memory Scatter-Gather Transfer __________________________________________ 6-8
6.5.5.
Peripheral Scatter-Gather Transfer ________________________________________ 6-11
6.6.
DMA Transfer Cycle _________________________________________________ 6-12
6.7.
Interrupts ________________________________________________________ 6-12
6.8.
Control Registers ___________________________________________________ 6-13
7.
I/O Ports (PPORT) _________________________________________________ 7-1
7.1.
Overview __________________________________________________________ 7-1
7.2.
I/O Cell Structure and Functions _______________________________________ 7-2
7.2.1.
Schmitt Input __________________________________________________________ 7-2
7.2.2.
Over Voltage Tolerant Fail-Safe Type I/O Cell _________________________________ 7-2
7.2.3.
Pull-Up/Pull-Down ______________________________________________________ 7-2
7.2.4.
CMOS Output and High Impedance State ___________________________________ 7-3
7.3.
Clock Settings ______________________________________________________ 7-3
7.3.1.
PPORT Operating Clock __________________________________________________ 7-3
7.3.2.
Clock Supply in SLEEP Mode _______________________________________________ 7-3
Seiko Epson Corporation
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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