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QSPICLKn
QSDIOn[3:0]
QSPI_nINTF.TBEIF
QSPI_nINTF.RBFIF
QSPI_nINTF.TENDIF
Data (W) → QSPI_nTXD
Software operations
Figure 15.5.5.1 Example of Data Receiving Operations in Register Access Master Mode
Data reception
Set the transfer direction to input
(QSPI_nCTL.DIR = 1)
Assert the slave select signal output from
the #QSPISSn pin (QSPI_nCTL.MSTSSO
= 0) or a general-purpose port
Read the QSPI_nINTF.TBEIF bit
QSPI_nINTF.TBEIF = 1 ?
Yes
Write dummy data (or transmit data) to
the QSPI_nTXD register
Wait for an interrupt request
(QSPI_nINTF.RBFIF = 1)
Read receive data from
the QSPI_nRXD register
Receive data remained?
No
Negate the slave select signal output from
the #QSPISSn pin (QSPI_nCTL.MSTSSO
= 1) or a general-purpose port
End
Figure 15.5.5.2 Data Reception Flowcharts in Register Access Master Mode
15-16
1
2
3
4
Data (W) → QSPI_nTXD
QSPI_nRXD → Data (R)
1 (W) → QSPI_nINTF.TENDIF
Not necessary
Set the transfer direction to input
in single
transfer mode
Assert the slave select signal output from
the #QSPISSn pin (QSPI_nCTL.MSTSSO
= 0) or a general-purpose port
Read the QSPI_nINTF.TBEIF bit
No
Write dummy data (or transmit data) to
Wait for an interrupt request
Write dummy data (or transmit data) to
Wait for an interrupt request
Yes
Negate the slave select signal output from
the #QSPISSn pin (QSPI_nCTL.MSTSSO
= 1) or a general-purpose port
Seiko Epson Corporation
1
2
3
4
1
2
QSPI_nRXD → Data (R)
Data (W) → QSPI_nTXD
Data reception
Not necessary
in single
(QSPI_nCTL.DIR = 1)
transfer modee
No
QSPI_nINTF.TBEIF = 1 ?
Yes
the QSPI_nTXD register
(QSPI_nINTF.TBEIF = 1)
the QSPI_nTXD register
(QSPI_nINTF.RBFIF = 1)
Read receive data from
the QSPI_nRXD register
Yes
Receive data remained?
No
End
3
4
QSPI_nRXD → Data (R)
Execute this sequence
within the QSPICLKn
cycles equivalent to
"Data bit length - 1" from
an interrupt request
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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