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19.7. Control Registers
ADC12A Ch.n Control Register
Register name
Bit
ADC12A_nCTL
15
14–12
11
10
9–8
7–2
1
0
Bit 15
Reserved
Bits 14–12
ADSTAT[2:0]
These bits indicate the analog input pin number m being A/D converted.
Table 19.7.1 Relationship Between Control Bit Value and Analog Input Pin
ADC12A_nCTL.ADSTAT[2:0] bits
ADC12A_nTRG.STAAIN[2:0] bits
ADC12A_nTRG.ENDAIN[2:0] bits
These bits indicate the last converted analog input pin number after A/D conversion is
forcefully terminated by writing 0 to the ADC12A_nCTL.ADST bit or automatically
terminated in one-time conversion mode (ADC12A_nTRG.CNVMD = 0). If A/D conversion
is stopped after the maximum analog input pin number (different in each model) has been
completed, these bits indicate ADINn0.
Bit 11
Reserved
Bit 10
BSYSTAT
This bit indicates whether the ADC12A is executing A/D conversion or not.
1 (R/W): A/D converting
0 (R/W): Idle
Bits 9–2
Reserved
Bit 1
ADST
This bit starts A/D conversion or enables to accept triggers. 1 (R/W): Start sampling and
conversion (software trigger)/Enable trigger acceptance (external trigger, 16-bit timer
underflow trigger) 0 (R/W): Terminate conversion
This bit does not revert to 0 automatically after A/D conversion has completed. Write 0 to
this bit once and write 1 again to start another A/D conversion. After 0 is written to this bit
to forcefully terminate conversion, the ADC12A stops after the A/D conversion being
executed is completed. Therefore, this bit cannot be used to determine whether the
ADC12A is executing A/D conversion or not.
Note:
The data written to the ADC12A_nCTL.ADST bit must be retained for one or more CLK_T16_k clock
cycles when 1 is written or two or more CLK_T16_k clock cycles when 0 is written.
Bit 0
MODEN
19-8
Bit name
Initial
–
0
ADSTAT[2:0]
0x0
–
0
BSYSTAT
0
–
0x0
–
0x00
ADST
0
MODEN
0
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
Seiko Epson Corporation
Reset
R/W
–
R
H0
R
–
R
H0
R
–
R
–
R
H0
R/W
H0
R/W
Analog input pin
ADINn7
ADINn6
ADINn5
ADINn4
ADINn3
ADINn2
ADINn1
ADINn0
Remarks
–
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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