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CLG System Clock Control Register
Register name
Bit
CLGSCLK
15
14
13–12
11–10
9–8
7–6
5–4
3–2
1–0
Bit 15
WUPMD
This bit enables the SYSCLK switching function at wake-up.
1 (R/WP):
0(R/WP):
When the CLGSCLK.WUPMD bit = 1, setting values of the CLGSCLK.WUPSRC[1:0] bits and
the CLGSCLK.WUPDIV[1:0] bits are loaded to the CLGSCLK.CLKSRC[1:0] bits and the
CLGSCLK. CLKDIV[1:0] bits, respectively, at wake-up from SLEEP mode to switch SYSCLK.
When the CLG- SCLK.WUPMD bit = 0, the CLGSCLK.CLKSRC[1:0] and
CLGSCLK.CLKDIV[1:0] bits are not altered at wake-up.
Bit 14
Reserved
Bits 13–12
WUPDIV[1:0]
These bits select the SYSCLK division ratio for resetting the CLGSCLK.CLKDIV[1:0] bits at
wake-up. This setting is ineffective when the CLGSCLK.WUPMD bit = 0.
Bits 11–10
Reserved
Bits 9–8
WUPSRC[1:0]
These bits select the SYSCLK clock source for resetting the CLGSCLK.CLKSRC[1:0] bits at
wake-up. When a currently stopped clock source is selected, it will automatically start
oscillating or clock input at wake-up. However, this setting is ineffective when the
CLGSCLK.WUPMD bit = 0.
Table 2.6.2 SYSCLK Clock Source and Division Ratio Settings at Wake-up
CLGSCLK.
WUPDIV[1:0] bits
0x3
0x2
0x1
0x0
Bits 7–6
Reserved
Bits 5–4
CLKDIV[1:0]
These bits set the division ratio of the clock source to determine the SYSCLK frequency.
Bits 3–2
Reserved
Bits 1–0
CLKSRC[1:0]
These bits select the SYSCLK clock source.
When a currently stopped clock source is selected, it will automatically start oscillating or
clock input.
Table 2.6.3 SYSCLK Clock Source and Division Ratio Settings
CLGSCLK.
CLKDIV[1:0] bits
0x3
0x2
0x1
0x0
CLG Oscillation Control Register
Register name
Bit
2-22
Bit name
Initial
WUPMD
0
–
0
WUPDIV[1:0]
0x0
–
0x0
WUPSRC[1:0]
0x0
–
0x0
CLKDIV[1:0]
0x2
–
0x0
CLKSRC[1:0]
0x0
Enable
Disable
CLGSCLK.WUPSRC[1:0] bits
0x0
IOSCCLK
OSC1CLK
1/8
Reserved
1/4
Reserved
1/2
1/1
CLGSCLK.CLKSRC[1:0] bits
0x0
IOSCCLK
OSC1CLK
1/8
Reserved
1/4
Reserved
1/2
1/1
Bit name
Initial
Seiko Epson Corporation
Reset
R/W
H0
R/WP
–
R
H0
R/WP
–
R
H0
R/WP
–
R
H0
R/WP
–
R
H0
R/WP
0x1
0x2
OSC3CLK
1/16
1/8
1/2
1/2
1/1
1/1
0x1
0x2
OSC3CLK
1/16
1/8
1/2
1/2
1/1
1/1
Reset
R/W
Remarks
–
0x3
EXOSCCLK
Reserved
Reserved
Reserved
1/1
0x3
EXOSCCLK
Reserved
Reserved
Reserved
1/1
Remarks
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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