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2. Power Supply, Reset, and Clocks
The power supply, reset, and clocks in this IC are managed by the embedded power generator, system
reset controller, and clock generator, respectively.
2.1. Power Generator (PWGA)
2.1.1. Overview
PWGA is the power generator that controls the internal power supply system to drive this IC with
stability and low power. The main features of PWGA are outlined below.
•
Embedded V
D1
The V
regulator generates the V
-
D1
keep current consumption constant independent of the V
The V
regulator supports two operation modes, normal mode and economy mode, and
-
D1
setting the V
operations.
The V
regulator supports two voltage modes, mode0 and mode1, and setting the V
-
D1
regulator into mode1 during low-speed operation helps achieve low-power operations.
•
VDDQSPI
VDDQSPI is the dedicate power supply for SPI-Flash interface and P9x PORT.
-
-
Figure 2.1.1.1 shows the PWGA configuration.
V
C
PW1
C
V
PW2
V
VDDQSPI
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
regulator
D1
regulator into economy mode at light loads helps achieve low-power
D1
PWGA
REGMODE[1:0]
DD
VD1
regulator
D1
SS
Figure 2.1.1.1 PWGA Configuration
Seiko Epson Corporation
voltage to drive internal circuits, this makes it possible to
voltage level.
DD
REGSEL
V
D1
REGDIS
D1
Internal circuits
QSPI Interface
2-1
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