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17.3. Clock Settings
17.3.1. T16B Operating Clock
When using T16B Ch.n, the T16B Ch.n operating clock CLK_T16Bn must be supplied to T16B Ch.n
from the clock generator. The CLK_T16Bn supply should be controlled as in the procedure shown below.
1. Enable the clock source in the clock generator if it is stopped (refer to "Clock Generator" in the
"Power Supply, Reset, and Clocks" chapter).
When an external clock is used, select the EXCLnm pin function (refer to the "I/O Ports" chapter).
2. Set the following T16B_nCLK register bits:
T16B_nCLK.CLKSRC[2:0] bits (Clock source selection)
-
T16B_nCLK.CLKDIV[3:0] bits (Clock division ratio selection = Clock frequency setting)
-
17.3.2. Clock Supply in SLEEP Mode
When using T16B during SLEEP mode, the T16B operating clock CLK_T16Bn must be configured so that it
will keep supplying by writing 0 to the CLGOSC.xxxxSLPC bit for the CLK_T16Bn clock source.
If the CLGOSC.xxxxSLPC bit for the CLK_T16Bn clock source is 1, the CLK_T16Bn clock source is
deactivated during SLEEP mode and T16B stops with the register settings and counter value maintained
at those before entering SLEEP mode. After the CPU returns to normal mode, CLK_T16Bn is supplied and
the T16B operation resumes.
17.3.3. Clock Supply During Debugging
The CLK_T16Bn supply during debugging should be controlled using the T16B_nCLK.DBRUN bit.
The CLK_T16Bn supply to T16B Ch.n is suspended when the CPU enters debug state if the
T16B_nCLK.DBRUN bit = 0. After the CPU returns to normal operation, the CLK_T16Bn supply resumes.
Although T16B Ch.n stops operating when the CLK_T16Bn supply is suspended, the counter and registers
retain the status before debug state was entered. If the T16B_nCLK.DBRUN bit = 1, the CLK_T16Bn supply
is not suspended and T16B Ch.n will keep operating in debug state.
17.3.4. Event Counter Clock
When EXCLnm is selected as the clock source using the T16B_nCLK.CLKSRC[2:0] bits, the channel
functions as a timer or event counter that counts the EXCLnm pin input clocks.
The counter counts rising edges of the input signal. This can be changed so that the counter will count
falling edges of the original signal by selecting EXCLnm inverted input as the clock source.
Note:
When running the counter using the event counter clock, two dummy clocks must be input before
the first counting up/down can be performed.
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
EXCLnm input
Counter
x
EXCLnm inverted input
Counter
x
Figure 17.3.4.1 Count Timing (During Count Up Operation)
Seiko Epson Corporation
x + 1
x + 2
x + 3
x + 1
x + 2
x + 3
17-3
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