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CLG FOUT Control Register
Register name
Bit
CLGFOUT
15–8
7
6–4
3–2
1
0
Bits 15–7
Reserved
Bits 6–4
FOUTDIV[2:0]
These bits set the FOUT clock division ratio.
Bits 3–2
FOUTSRC[1:0]
These bits select the FOUT clock source.
Table 2.6.13 FOUT Clock Source and Division Ratio Settings
CLGFOUT.
FOUTDIV[2:0] bits
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
Note: When the CLGFOUT.FOUTSRC[1:0] bits are set to 0x3, the FOUT output will be
stopped in SLEEP/HALT mode as SYSCLK is stopped.
Bit 1
Reserved
Bit 0
FOUTEN
This bit controls the FOUT clock external output.
1 (R/W):
0 (R/W):
Note:
Since the FOUT signal generated is out of sync with writings to the CLGFOUT.FOUTEN bit, a glitch may
occur when the FOUT output is enabled or disabled.
2-30
Bit name
Initial
–
0x00
–
0
FOUTDIV[2:0]
0x0
FOUTSRC[1:0]
0x0
–
0
FOUTEN
0
CLGFOUT.FOUTSRC[1:0] bits
0x0
IOSCCLK
OSC1CLK
1/128
1/32,768
1/64
1/4,096
1/32
1/1,024
1/16
1/8
1/4
1/2
1/1
Enable external output
Disable external output
Seiko Epson Corporation
Reset
R/W
–
R
–
R
H0
R/W
H0
R/W
–
R
H0
R/W
0x1
0x2
OSC3CLK
1/128
1/64
1/32
1/256
1/16
1/8
1/8
1/4
1/4
1/2
1/2
1/1
1/1
Remarks
–
0x3
SYSCLK
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1/1
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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