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15.5.9. Data Transfer in Slave Mode
A data sending/receiving procedure and operations in slave mode are shown below. Figures 15.5.9.1
and 15.5.9.2 show a timing chart and flowcharts, respectively.
Data sending procedure
1. Check to see if the QSPI_nINTF.TBEIF bit is set to 1 (transmit buffer empty).
2. Write transmit data to the QSPI_nTXD register.
3. Wait for a transmit buffer empty interrupt (QSPI_nINTF.TBEIF bit = 1).
4. Repeat Steps 2 and 3 until the end of transmit data.
Note:
Transmit data must be written to the QSPI_nTXD register after the QSPI_nINTF.TBEIF bit is set to 1
by the time the sending QSPI_nTXD register data written is completed. If no transmit data is written
during this period, the data bits input from the QSDIOn pins are shifted and output from the
QSDIOn pins without being modified.
Data receiving procedure
1. Wait for a receive buffer full interrupt (QSPI_nINTF.RBFIF bit = 1).
2. Read the received data from the QSPI_nRXD register.
3. Repeat Steps 1 and 2 until the end of data reception.
Data transfer operations
The following shows the slave mode operations different from master mode:
•
Slave mode operates with the QSPI clock supplied from the external QSPI master to the QSPICLKn
pin. The data transfer rate is determined by the QSPICLKn frequency. It is not necessary to control
the 16-bit timer.
•
QSPI can operate as a slave device only when the slave select signal input from the external
QSPI master to the #QSPISSn pin is set to the active (low) level. If #QSPISSn = high, the
software transfer control, the QSPICLKn pin input, and the QSDIOn pins input are all ineffective. If
the #QSPISSn signal goes high during data transfer, the transfer bit counter is cleared and data in
the shift register is discarded.
•
Slave mode starts data transfer when QSPICLKn is input from the external QSPI master after the
#QSPISSn signal is asserted. Writing transmit data is not a trigger to start data transfer. Therefore,
it is not necessary to write dummy data to the transmit data buffer when performing data
reception only.
•
Data transmission/reception can be performed even in SLEEP mode, it makes it possible to wake
the CPU up using a QSPI interrupt.
Other operations are the same as master mode.
Notes:
•
If data of the number of cycles specified by the QSPI_nMOD.CHLN[3:0] bits is received when the
QSPI_nINTF.RBFIF bit is set to 1, the QSPI_nRXD register is overwritten with the newly received data
and the previously received data is lost. In this case, the QSPI_nINTF.OEIF bit is set.
•
When the clock for the first bit is input from the QSPICLKn pin, QSPI starts sending the data
currently stored in the shift register even if the QSPI_nINTF.TBEIF bit is set to 1.
15-28
Seiko Epson Corporation
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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