Page 1 CMOS 32-BIT SINGLE CHIP MICROCONTROLLER S1C31D41 Technical Manual Rev. 1.1...
Page 2 2. This evaluation board/kit or development tool is intended for use by an electronic engineer and is not a consumer product. The user should use it properly and in a safe manner. Seiko Epson does not assume any responsibility or liability of any kind of damage and/or fire caused by its use.
Page 3 Low power mode This manual describes the low power modes as HALT mode and SLEEP mode. These terms refer to sleep mode and deep sleep mode in the Cortex -M0+ processor, respectively. ® Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 4: Table Of Contents
3 CPU and Debugger ......................3-1 3.1 Overview ......................... 3-1 3.2 CPU ..........................3-1 3.3 Debugger ........................3-1 3.3.1 List of Debugger Input/Output Pins ..............3-1 3.3.2 External Connection ..................3-1 3.4 Reference Documents ....................3-2 Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 5 DMAC Software Request Register ..................6-11 DMAC Request Mask Set Register ..................6-11 DMAC Request Mask Clear Register ................. 6-12 DMAC Enable Set Register....................6-12 DMAC Enable Clear Register ..................... 6-12 DMAC Primary-Alternate Set Register ................6-12 Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 6 8.1 Overview ......................... 8-1 8.2 Peripheral Circuit I/O Function Assignment ..............8-1 8.3 Control Registers ......................8-2 Pxy–xz Universal Port Multiplexer Setting Register ............. 8-2 9 Watchdog Timer (WDT2) ....................9-1 9.1 Overview ......................... 9-1 Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 7 11.4.2 SVD3 Operations ................... 11-4 11.5 SVD3 Interrupt and Reset .................... 11-4 11.5.1 SVD3 Interrupt ....................11-4 11.5.2 SVD3 Reset ....................11-5 11.6 Control Registers ......................11-5 SVD3 Clock Control Register ..................... 11-5 Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 8 13.5.5 Carrier Modulation ..................13-8 13.6 Receive Errors ......................13-9 13.6.1 Framing Error ....................13-9 13.6.2 Parity Error ..................... 13-9 13.6.3 Overrun Error ....................13-9 13.7 Interrupts ........................13-10 13.8 DMA Transfer Requests ....................13-10 Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 9 15.2.4 Input Pin Pull-Up/Pull-Down Function ............15-6 15.3 Clock Settings ......................15-6 15.3.1 QSPI Operating Clock ................... 15-6 15.3.2 Clock Supply During Debugging ..............15-7 15.3.3 QSPI Clock (QSPICLKn) Phase and Polarity ..........15-7 Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 10 16.5 Interrupts ........................16-17 16.6 DMA Transfer Requests ....................16-18 16.7 Control Registers ......................16-18 I2C Ch.n Clock Control Register ..................16-18 I2C Ch.n Mode Register ....................16-19 I2C Ch.n Baud-Rate Register .................... 16-19 Seiko Epson Corporation viii S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 11 18.4.3 REMO Output Waveform ................18-3 18.4.4 Continuous Data Transmission and Compare Buffers........18-5 18.5 Interrupts ........................18-6 18.6 Application Example: Driving EL Lamp ................ 18-7 18.7 Control Registers ......................18-7 REMC3 Clock Control Register ..................18-7 Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 12 21.2.2 External Connections ..................21-2 21.3 Clock Settings ......................21-3 21.3.1 RFC Operating Clock ..................21-3 21.3.2 Clock Supply in SLEEP Mode ............... 21-3 21.3.3 Clock Supply in DEBUG Mode ..............21-3 Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 13 Interrupt Mask Register ..................... 22-25 Memory Address Register ....................22-25 Memory Size Register......................22-26 Initial Value Setting Register ....................22-26 Command Register ......................22-26 State Monitor Register ....................... 22-26 Error Status Register ......................22-27 Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 14 16-bit Timer (T16) Ch.1 ........... AP-A-22 0x0020 03b0–0x0020 03be Synchronous Serial Interface (SPIA) Ch.0 ....AP-A-23 0x0020 03c0–0x0020 03d6 C (I2C) Ch.0 ............AP-A-24 0x0020 0400–0x0020 042c 16-bit PWM Timer (T16B) Ch.0 ....... AP-A-25 Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 15 B.1 Operating Status Configuration Examples for Power Saving ........AP-B-1 B.2 Other Power Saving Methods ..................AP-B-2 Appendix C Mounting Precautions ................AP-C-1 Appendix D Measures Against Noise ................ AP-D-1 Revision History Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL xiii (Rev. 1.1)
Page 16: Overview
Instruction cache 512 bytes HW processor (HWP) Sound play function Sound algorithm EPSON high quality and high compression algorithm (EOV: EPSON Original Sound Format) Playback channels 2 channels with mixing supported (e.g. Ch.0: voice, Ch.1: BGM) Sampling frequency 15.625 kHz...
Page 17 Reset when the watchdog timer overflows (can be enabled/disabled using a register). Supply voltage detector reset Reset when the supply voltage detector detects the set voltage level (can be enabled/dis- abled using a register). Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 18 -M0+ processor. The RAM retains data even in SLEEP mode. ® *3 HALT mode refers to sleep mode in the Cortex -M0+ processor. ® *4 Shown in parentheses are JEITA package names. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 19: Block Diagram
3 Ch. SDACOUT_P, P2 * (SDAC2) SDACOUT_N, N2 * 1 Ch. * The pin configuration depends on the package. For detailed information, refer to Section 1.3, “Pins.” Figure 1.2.1 S1C31D41 Block Diagram Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 20: Pins
TQFP12-32PIN Port function or signal assignment Pin name #RESET P43/RTC1S #RESET P42/#ADTRG0 P54/EXOSC P17/UPMUX/VREFA0 P31/EXCL10/UPMUX P16/UPMUX/ADIN00 P15/UPMUX/ADIN01 P32/EXCL11/UPMUX SWCLK/PD0 P14/UPMUX/ADIN02 SWD/PD1 P13/FOUT/UPMUX/ADIN03 P12/UPMUX/ADIN04 TEST TEST Figure 1.3.1.1 S1C31D41 Pin Configuration Diagram (TQFP12-32PIN) Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 21 P43/RTC1S P42/#ADTRG0 P17/UPMUX/VREFA0 OSC1 OSC1 P16/UPMUX/ADIN00 OSC2 OSC2 P54/EXOSC P15/UPMUX/ADIN01 P55/EXCL00 P14/UPMUX/ADIN02 P56/EXCL01 P13/FOUT/UPMUX/ADIN03 P31/EXCL10/UPMUX P12/UPMUX/ADIN04 P32/EXCL11/UPMUX P06/SDACOUT_N2/UPMUX P05/SDACOUT_N/UPMUX SWCLK/PD0 P04/SDACOUT_P/UPMUX SWD/PD1 TEST TEST P03/SDACOUT_P2/UPMUX Figure 1.3.1.2 S1C31D41 Pin Configuration Diagram (TQFP12-48PIN) Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 22 OSC2 OSC2 P17/UPMUX/VREFA0 P16/UPMUX/ADIN00 P15/UPMUX/ADIN01 P54/EXOSC P55/EXCL00 P14/UPMUX/ADIN02 P56/EXCL01 P13/FOUT/UPMUX/ADIN03 P07/UPMUX P12/UPMUX/ADIN04 P11/UPMUX/ADIN05 P30/UPMUX P31/EXCL10/UPMUX P10/UPMUX/ADIN06 P32/EXCL11/UPMUX P06/SDACOUT_N2/UPMUX SWCLK/PD0 P05/SDACOUT_N/UPMUX SWD/PD1 P04/SDACOUT_P/UPMUX TEST TEST P03/SDACOUT_P2/UPMUX Figure 1.3.1.3 S1C31D41 Pin Configuration Diagram (QFP13-64PIN) Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 23: Pin Descriptions
User-selected I/O (universal port multiplexer) ADIN05 12-bit A/D converter Ch.0 analog signal input 5 Hi-Z – I/O port ✓ ✓ ✓ UPMUX User-selected I/O (universal port multiplexer) ADIN04 12-bit A/D converter Ch.0 analog signal input 4 Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 24 12-bit A/D converter Ch.0 trigger input Hi-Z – I/O port ✓ ✓ ✓ RTC1S Real-time clock 1-second cycle pulse output Hi-Z I/O port ✓ ✓ ✓ ✓ EXSVD0 Supply voltage detector external voltage detection input 0 Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 25 T16B Ch.n PWM output/capture input 1 TOUTn2/CAPn2 T16B Ch.n PWM output/capture input 2 TOUTn3/CAPn3 T16B Ch.n PWM output/capture input 3 Note: Do not assign a function to two or more pins simultaneously. Seiko Epson Corporation 1-10 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 26: Power Supply, Reset, And Clocks
Connection Diagram” chapter, respectively. DDQSPI is the power supply dedicated for the quad synchronous serial interface (QSPI-Flash). It is also used as DDQSPI the power supply for the I/O ports P60 to P65. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 27: D1 Regulator Operation Mode
(Set to automatic mode) 5. Switch the system clock to a high-speed clock. 6. Write a value other than 0x0096 to the SYSPROT.PROT[15:0] bits. (Set system protection) Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 28: System Reset Controller (Src)
Reset request from CPU Watchdog timer reset Supply voltage detector reset SYSRST_S0_0 Software reset 0 To peripheral circuit 0 Reset decoder SYSRST_S0_n Software reset n To peripheral circuit n Figure 2.2.1.1 SRC Configuration Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 29: Input Pin
Note, however, that the software reset operations depend on the periph- eral circuit. For more information, refer to “Control Registers” in each peripheral circuit chapter. Note: The MODEN bit of some peripheral circuits does not issue software reset. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 30: Initialization Conditions (Reset Groups)
OSC1 crystal oscillator circuit Unavailable Available Available OSC1 internal oscillator circuit Available Available Available OSC2 crystal/ceramic oscillator circuit Available Available Available OSC3 internal oscillator circuit Available Available Available EXOSC clock input Available Available Available Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 31: Input/Output Pins
2.3.3 Clock Sources IOSC oscillator circuit The IOSC oscillator circuit features a fast startup and no external parts are required for oscillating. Figure 2.3.3.1 shows the configuration of the IOSC oscillator circuit. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 32 OSC3 pin open. For the recommended parts and the oscillation characteristics, refer to the “Basic External Connection Diagram” chapter and “OSC1 oscillator circuit characteristics” in the “Electrical Characteristics” chapter, respectively. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 33 EXOSC has no oscillation stabilization waiting circuit included, therefore, it must be enabled when a stabilized clock is being supplied. For the input clock characteristics, refer to “EXOSC external clock input characteris- tics” in the “Electrical Characteristics” chapter. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 34: Operations
Figure 2.3.4.2 shows an operation example when the oscillation start- up control circuit is used. (1) CLGOSC1.OSC1BUP bit = 0 (startup boosting operation disabled) Oscillator circuit enable (CLGOSC.OSC1EN) Oscillation inverter INV1N[1:0] setting gain Oscillation waveform Normal operation Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 35 CLGOSC1.INV1B[1:0], and CLGTRIM2.OSC1SAJ[5:0] bits should be determined after performing evaluation using the populated circuit board. Note: Make sure the CLGOSC.OSC1EN bit is set to 0 (while the OSC1 oscillation is halted) when set- ting the CLGTRIM2.OSC1SAJ[5:0] bits. Seiko Epson Corporation 2-10 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 36 RUN mode, and the peripheral circuits to continue operating without disabling the clock in SLEEP mode. The CLGOSC.IOSCSLPC, CLGOSC.OSC1SLPC, CLGOSC.OSC3SLPC, and CLGOSC.EXOSCSLPC bits are used for this control. Figure 2.3.4.3 shows a control example. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 2-11...
Page 37 OSC1CLK clock generated by the OSC1 oscillator circuit (crystal oscillator). However, this function is effective only when 16 MHz (CLGOSC3.OSC3FQ[1:0] bits = 0x3) has been selected to the OSC3 oscillation frequency. Seiko Epson Corporation 2-12 S1C31D41 TECHNICAL MANUAL...
Page 38 7. The OSC1 oscillation stops if the CLGINTF.OSC1STPIF bit = 1 after an interrupt occurs. If the CLGOSC1.OSDRB bit = 1, the hardware restarts the OSC1 oscillator circuit. Note: Enabling the oscillation stop detection function increase the oscillation stop detector current (I OSD1 Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 2-13 (Rev. 1.1)
Page 39: Operating Mode
0 keeps operating, so the peripheral circuits with the clock being supplied can also operate. By setting this mode when no software processing and peripheral circuit operations are required, power consumption can be less than HALT mode. The RAM retains data even in SLEEP mode. Seiko Epson Corporation 2-14 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 40 The conditions listed below generate the HALT/SLEEP cancelation signal to cancel HALT or SLEEP mode and put the CPU into RUN mode. • Interrupt request from a peripheral circuit • NMI from the watchdog timer • Reset request Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 2-15 (Rev. 1.1)
Page 41: Interrupts
Bits 3–2 Reserved Bits 1–0 REGMODE[1:0] These bits control the V regulator operating mode. Table 2.6.1 Internal Regulator Operating Mode PWGACTL.REGMODE[1:0] bits Operating mode Economy mode Normal mode Reserved Automatic mode Seiko Epson Corporation 2-16 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 42: Clg System Clock Control Register
These bits set the division ratio of the clock source to determine the SYSCLK frequency. Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the SYSCLK clock source. When a currently stopped clock source is selected, it will automatically start oscillating or clock input. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 2-17 (Rev. 1.1)
Page 43: Clg Oscillation Control Register
Stop oscillating or clock input Each bit corresponds to the clock source as follows: CLGOSC.EXOSCEN bit: EXOSC clock input CLGOSC.OSC3EN bit: OSC3 oscillator circuit CLGOSC.OSC1EN bit: OSC1 oscillator circuit CLGOSC.IOSCEN bit: IOSC oscillator circuit Seiko Epson Corporation 2-18 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 44: Clg Iosc Control Register
This bit selects an oscillator type of the OSC1 oscillator circuit. 1 (R/WP): Internal oscillator 0 (R/WP): Crystal oscillator Bits 10–8 CGI1[2:0] These bits set the internal gate capacitance in the OSC1 oscillator circuit. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 2-19 (Rev. 1.1)
Page 45: Clg Osc3 Control Register
Bit name Initial Reset Remarks CLGOSC3 15–12 – – – 11–10 OSC3FQ[1:0] R/WP OSC3MD R/WP – – 7–6 – – 5–4 OSC3INV[1:0] R/WP OSC3STM R/WP 2–0 OSC3WT[2:0] R/WP Bits 15–12 Reserved Seiko Epson Corporation 2-20 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 46 These bits set the oscillation stabilization waiting time for the OSC3 oscillator circuit. Table 2.6.11 OSC3 Oscillation Stabilization Waiting Time Setting CLGOSC3.OSC3WT[2:0] bits Oscillation stabilization waiting time 65,536 clocks 16,384 clocks 8,192 clocks 4,096 clocks 0x3–0x0 Setting prohibited Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 2-21 (Rev. 1.1)
Page 47: Clg Interrupt Flag Register
CLG Interrupt Enable Register Register name Bit name Initial Reset Remarks CLGINTE 15–9 – 0x00 – – OSC3TERIE – – (reserved) OSC1STPIE OSC3TEDIE – – OSC3STAIE OSC1STAIE IOSCSTAIE Bits 15–9, 7, 6, 3 Reserved Seiko Epson Corporation 2-22 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 48: Clg Fout Control Register
0 (R/W): Disable external output Note: Since the FOUT signal generated is out of sync with writings to the CLGFOUT.FOUTEN bit, a glitch may occur when the FOUT output is enabled or disabled. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 2-23...
Page 49: Clg Oscillation Frequency Trimming Register 1
“Electrical Characteristics” chapter can be guaranteed. Be aware that the frequency characteristic may not be satisfied when this setting is altered. When altering this setting, always make sure that the OSC1 oscillator circuit is inactive. Seiko Epson Corporation 2-24 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 50: Clg Oscillation Frequency Trimming Register 3
“Electrical Characteristics” chapter can be guaranteed. Be aware that the frequency characteristic may not be satisfied when this setting is altered. When altering this setting, always make sure that the OSC3 oscillator circuit is inactive. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 2-25 (Rev. 1.1)
Page 51: Cpu And Debugger
For the recommended pull-up resistor value, refer to “Recommended Operating Conditions, Debug pin pull-up re- sistors R ” in the “Electrical Characteristics” chapter. R and R are not required when using the debug DBG1–2 DBG1 DBG2 pins as general-purpose I/O port pins. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 52: Reference Documents
Architecture Reference Manual ® 2. Cortex -M0+Technical Reference Manual ® 3. Cortex -M0+ Devices Generic User Guide ® These documents can be downloaded from the document site of Arm Ltd. https://developer.arm.com/documentation Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 53: Memory And Bus
Flash memory (1M bytes) (Device size: 32 bits) 0x0004 0000 0x0003 ffff Reserved 0x0001 8000 0x0001 7fff Flash area (96K bytes) (Device size: 32 bits) 0x0000 0000 Figure 4.1.1 Memory Map Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 54: Bus Access Cycle
Notes: • When programming the Flash memory, 2.2 V or more V voltage is required. • Be sure to avoid using the V pin output for driving external circuits. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 55: Ram
P0 Port Mode Select Register 0x0020 020e PPORTP0FNCSEL P0 Port Function Select Register 0x0020 0210 PPORTP1DAT P1 Port Data Register 0x0020 0212 PPORTP1IOEN P1 Port Enable Register 0x0020 0214 PPORTP1RCTL P1 Port Pull-up/down Control Register Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 56 P20–21 Universal Port Multiplexer Setting Register 0x0020 0312 UPMUXP2MUX1 P22–23 Universal Port Multiplexer Setting Register 0x0020 0314 UPMUXP2MUX2 P24–25 Universal Port Multiplexer Setting Register 0x0020 0316 UPMUXP2MUX3 P26–27 Universal Port Multiplexer Setting Register Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 57 0x0020 042c T16B_0CC3DMAEN T16B Ch.0 Compare/Capture 3 DMA Request Enable Register 16-bit PWM timer (T16B) 0x0020 0440 T16B_1CLK T16B Ch.1 Clock Control Register Ch.1 0x0020 0442 T16B_1CTL T16B Ch.1 Counter Control Register Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 58 UART3 Ch.2 Clock Control Register 0x0020 0622 UART3_2MOD UART3 Ch.2 Mode Register 0x0020 0624 UART3_2BR UART3 Ch.2 Baud-Rate Register 0x0020 0626 UART3_2CTL UART3 Ch.2 Control Register 0x0020 0628 UART3_2TXD UART3 Ch.2 Transmit Data Register Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 59 0x0020 06f2 I2C_2INTE I2C Ch.2 Interrupt Enable Register 0x0020 06f4 I2C_2TBEDMAEN I2C Ch.2 Transmit Buffer Empty DMA Request Enable Register 0x0020 06f6 I2C_2RBFDMAEN I2C Ch.2 Receive Buffer Full DMA Request Enable Register Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 60 DMAC Enable Set Register 0x0020 102c DMACENCLR DMAC Enable Clear Register 0x0020 1030 DMACPASET DMAC Primary-Alternate Set Register 0x0020 1034 DMACPACLR DMAC Primary-Alternate Clear Register 0x0020 1038 DMACPRSET DMAC Priority Set Register Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 61: System-Protect Function
“WP” or “R/WP” appearing in the R/W column). CACHE Control Register Register name Bit name Initial Reset Remarks CACHECTL 15–8 – 0x00 – – 7–2 – 0x00 – – – CACHEEN Bits 15–1 Reserved Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 62: Flashc Flash Read Cycle Register
Notes: • Be sure to set the FLASHCWAIT.RDWAIT[1:0] bits before the system clock is configured. • When the FLASHCWAIT.RDWAIT[1:0] bit setting is altered from 0x2 to 0x1, add two NOP instructions immediately after that. Program example: FLASHC->WAIT_b.RDWAIT = 1; asm(“NOP”); asm(“NOP”); CLG->OSC_b.IOSCEN = 0; Seiko Epson Corporation 4-10 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 63: Interrupt
• IOSC oscillation stabilization waiting completion • OSC1 oscillation stabilization waiting completion • OSC3 oscillation stabilization waiting completion • OSC1 oscillation stop • OSC3 oscillation auto-trimming completion • OSC3 oscillation auto-trimming error Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 64 • Overrun error • Receive buﬀer two bytes full • Receive buﬀer one byte full • Transmit buﬀer empty 16-bit timer Ch.0 interrupt Underﬂow VTOR + 0x90 16-bit timer Ch.3 interrupt Underﬂow Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 65: Vector Table Offset Address (Vtor)
CPU even if the interrupt flag is set to 1. An interrupt request is also sent to the CPU if the status is changed to interrupt enabled when the interrupt flag is 1. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL...
Page 66: Nmi
The watchdog timer embedded in this IC can generate a non-maskable interrupt (NMI). This interrupt takes prece- dence over other interrupts and is unconditionally accepted by the CPU. For detailed information on generating NMI, refer to the “Watchdog Timer” chapter. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 67: Dma Controller (Dmac)
Bus matrix PASETn PACLRn Peripheral circuit PRSETn SWREQn PRCLRn DMA transfer request Peripheral circuit ENDIESETn ENDIFn Interrupt DMA transfer request ENDIECLRn control circuit ERRIESET ERRIF ERRIECLR Figure 6.1.1 DMAC Configuration Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 68: Operations
256 bytes DMACCPTR.CPTR[31:0] (CPTR[7:0] = 0x00) DMACCPTR.CPTR[31:0] + 0x080 9 to 16 512 bytes DMACCPTR.CPTR[31:0] (CPTR[8:0] = 0x000) DMACCPTR.CPTR[31:0] + 0x100 17 to 32 1,024 bytes DMACCPTR.CPTR[31:0] (CPTR[9:0] = 0x000) DMACCPTR.CPTR[31:0] + 0x200 Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 69: Transfer Source End Pointer
6.4.2 Transfer Destination End Pointer Set the address to which the last transfer data is written. The address for writing transfer data should be set as it is if the transfer destination address is not incremented. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 70 DMA transfer for the channel with the highest priority. If the arbitration cycle setting value is larger than the number of successive data transfers, successive data trans- fers will not be suspended. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 71: Dma Transfer Mode
DMA transfer 1 DMA transfer 2 DMA transfer 3 DMA transfer 4 DMA transfer 7 DMA transfer 8 operation DMACENDIF.ENDIFn DMA transfer request Figure 6.5.2.1 Auto-Request Transfer Operation Example (N = 8, 2 = 2) Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 72: Ping-Pong Transfer
5. Set cycle_ctrl to 0x0 after a DMA transfer completion interrupt has occurred by the next to last task. 6. The DMA transfer is completed when a DMA transfer completion interrupt occurs by the last task. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL...
Page 73: Memory Scatter-Gather Transfer
Copy the data structure for Task D to the alternate data structure. (cycle_ctrl = 0x1, 2 = 4, N = 4) Task D DMA transfer completion interrupt Figure 6.5.4.2 Memory Scatter-Gather Transfer Operation Example Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 74: Peripheral Scatter-Gather Transfer
Copy the data structure for Task D to the alternate data structure. (cycle_ctrl = 0x1, 2 = 4, N = 4) Task D DMA transfer completion interrupt Figure 6.5.5.1 Peripheral Scatter-Gather Transfer Operation Example Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 75: Dma Transfer Cycle
The DMAC provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the CPU only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For more information on interrupt control, refer to the “Interrupt” chapter. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 76: Control Registers
– 15–8 – 0x00 – – 7–1 – 0x00 – MSTEN – – Bits 31–1 Reserved Bit 0 MSTEN This bit enables the DMA controller. 1 (W): Enable 0 (W): Disable Seiko Epson Corporation 6-10 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 77: Dmac Control Data Base Pointer Register
DMA transfer requests from peripheral circuits have been disabled. 0 (R): DMA transfer requests from peripheral circuits have been enabled. Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented channels are ineffective. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 6-11 (Rev. 1.1)
Page 78: Dmac Request Mask Clear Register
The alternate data structure has been enabled. 0 (R): The primary data structure has been enabled. Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented channels are ineffective. Seiko Epson Corporation 6-12 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 79: Dmac Primary-Alternate Clear Register
ERRIF This bit indicates the DMAC error interrupt cause occurrence status. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 6-13 (Rev. 1.1)
Page 80: Dmac Transfer Completion Interrupt Flag Register
DMAC Error Interrupt Enable Set Register Register name Bit name Initial Reset Remarks DMACERRIESET 31–24 – 0x00 – – 23–16 – 0x00 – 15–8 – 0x00 – 7–1 – 0x00 – ERRIESET Bits 31–1 Reserved Seiko Epson Corporation 6-14 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 81: Dmac Error Interrupt Enable Clear Register
0x00 – ERRIECLR – – Bits 31–1 Reserved Bit 0 ERRIECLR This bit disables DMA error interrupts. 1 (W): Disable interrupt (The DMACERRIESET register is cleared to 0.) 0 (W): Ineffective Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 6-15 (Rev. 1.1)
Page 82: O Ports (Pport)
Pd[3:0] Total number of ports 25 ports 39 ports 55 ports Ports for debug function Pd[1:0] Key-entry reset function Unavailable *1 Ports with general-purpose I/O function (GPIO) *2 Ports with interrupt function Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 83: I/O Cell Structure And Functions
The input functions are all configured with the Schmitt interface level. When a port is set to input disable status (PPORTPxIOEN.PxIENy bit = 0), unnecessary current is not consumed if the Pxy pin is placed into floating status. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL...
Page 84: Over Voltage Tolerant Fail-Safe Type I/O Cell
When using the chattering filter function during SLEEP mode, the PPORT operating clock CLK_PPORT must be configured so that it will keep suppling by writing 0 to the CLGOSC.xxxxSLPC bit for the CLK_PPORT clock source. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 85: Clock Supply During Debugging
When using the Pxy port pin as a general-purpose output pin, perform the following software initial settings: 1. Set the PPORTPxIOEN.PxOENy bit to 1. (Enable output) 2. Set the PPORTPxMODSEL.PxSELy bit to 0. (Enable GPIO function) Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 86: Port Input/Output Control
7.4.2 Port Input/Output Control Peripheral I/O function control The port for which a peripheral I/O function is selected is controlled by the peripheral circuit. For more infor- mation, refer to the respective peripheral circuit chapter. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 87: Interrupts
CPU only when the interrupt flag, of which interrupt has been enabled by the in- terrupt enable bit, is set. For more information on interrupt control, refer to the “Interrupt” chapter. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL...
Page 88: Control Registers
When both data output and data input are enabled, the pin output status controlled by this IC can be read. These bits do not affect the input control when the port is used as a peripheral I/O function. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 89: Px Port Pull-Up/Down Control Register
These bits select the input signal edge to generate a port input interrupt. 1 (R/W): An interrupt will occur at a falling edge. 0 (R/W): An interrupt will occur at a rising edge. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 90: Px Port Chattering Filter Enable Register
These bits select the peripheral I/O function to be assigned to each port pin. Table 7.6.1 Selecting Peripheral I/O Function PPORTPxFNCSEL.PxyMUX[1:0] bits Peripheral I/O function Function 3 Function 2 Function 1 Function 0 This selection takes effect when the PPORTPxMODSEL.PxSELy bit = 1. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 91: P Port Clock Control Register
1/32,768 1/16,384 1/8,192 1/4,096 1/2,048 1/1,024 1/512 1/256 1/128 1/64 1/32 1/16 (Note) The oscillation circuits/external input that are not supported in this IC cannot be selected as the clock source. Seiko Epson Corporation 7-10 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 92: P Port Interrupt Flag Group Register
A port generated an interrupt 0 (R): No port generated an interrupt The PPORTINTFGRP.PxINT bit is cleared when the interrupt flag for the port that has generated an interrupt is cleared. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 7-11 (Rev. 1.1)
Page 93: Control Register And Port Function Configuration Of This Ic
– – ✓ P0REN6 – ✓ ✓ P0REN5 – ✓ ✓ P0REN4 – ✓ ✓ P0REN3 – ✓ ✓ P0REN2 – ✓ ✓ P0REN1 – – ✓ P0REN0 – – ✓ Seiko Epson Corporation 7-12 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 94 Select Register) 11–10 P05MUX[1:0] – ✓ ✓ 9–8 P04MUX[1:0] – ✓ ✓ 7–6 P03MUX[1:0] – ✓ ✓ 5–4 P02MUX[1:0] – ✓ ✓ 3–2 P01MUX[1:0] – – ✓ 1–0 P00MUX[1:0] – – ✓ Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 7-13 (Rev. 1.1)
Page 95: P1 Port Group
✓ ✓ ✓ P1OEN6 ✓ ✓ ✓ P1OEN5 ✓ ✓ ✓ P1OEN4 ✓ ✓ ✓ P1OEN3 ✓ ✓ ✓ P1OEN2 ✓ ✓ ✓ P1OEN1 – – ✓ P1OEN0 – – ✓ Seiko Epson Corporation 7-14 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 96 Filter Enable Register) P1CHATEN6 ✓ ✓ ✓ P1CHATEN5 ✓ ✓ ✓ P1CHATEN4 ✓ ✓ ✓ P1CHATEN3 ✓ ✓ ✓ P1CHATEN2 ✓ ✓ ✓ P1CHATEN1 – – ✓ P1CHATEN0 – – ✓ Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 7-15 (Rev. 1.1)
Page 97: P2 Port Group
– – ✓ P2IN6 – – ✓ P2IN5 – – ✓ P2IN4 – – ✓ P2IN3 – ✓ ✓ P2IN2 – ✓ ✓ P2IN1 – ✓ ✓ P2IN0 ✓ ✓ ✓ Seiko Epson Corporation 7-16 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 98 – – ✓ P2IE6 – – ✓ P2IE5 – – ✓ P2IE4 – – ✓ P2IE3 – ✓ ✓ P2IE2 – ✓ ✓ P2IE1 – ✓ ✓ P2IE0 ✓ ✓ ✓ Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 7-17 (Rev. 1.1)
Page 99 – – ✓ – – UPMUX – – – – – – ✓ – – UPMUX – – – – – – ✓ *1: Refer to the “Universal Port Multiplexer” chapter. Seiko Epson Corporation 7-18 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 100: P3 Port Group
– – ✓ P3REN6 – – ✓ P3REN5 – ✓ ✓ P3REN4 – ✓ ✓ P3REN3 – ✓ ✓ P3REN2 ✓ ✓ ✓ P3REN1 ✓ ✓ ✓ P3REN0 – – ✓ Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 7-19 (Rev. 1.1)
Page 101 Select Register) 11–10 P35MUX[1:0] – ✓ ✓ 9–8 P34MUX[1:0] – ✓ ✓ 7–6 P33MUX[1:0] – ✓ ✓ 5–4 P32MUX[1:0] ✓ ✓ ✓ 3–2 P31MUX[1:0] ✓ ✓ ✓ 1–0 P30MUX[1:0] – – ✓ Seiko Epson Corporation 7-20 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 102: P4 Port Group
7–6 – – – – – – P4OEN5 – – ✓ ✓ P4OEN4 ✓ ✓ ✓ P4OEN3 ✓ ✓ ✓ P4OEN2 ✓ ✓ ✓ P4OEN1 – – ✓ P4OEN0 – – ✓ Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 7-21 (Rev. 1.1)
Page 103 7–6 – – – – – Register) P4SEL5 – – ✓ ✓ P4SEL4 ✓ ✓ ✓ P4SEL3 ✓ ✓ ✓ P4SEL2 ✓ ✓ ✓ P4SEL1 – – ✓ P4SEL0 – – ✓ Seiko Epson Corporation 7-22 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 104: P5 Port Group
– – P5OEN6 – – ✓ ✓ P5OEN5 – ✓ ✓ P5OEN4 ✓ ✓ ✓ P5OEN3 – – ✓ P5OEN2 – – ✓ P5OEN1 ✓ ✓ ✓ P5OEN0 ✓ ✓ ✓ Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 7-23 (Rev. 1.1)
Page 105 Filter Enable Register) P5CHATEN6 – – ✓ ✓ P5CHATEN5 – ✓ ✓ P5CHATEN4 ✓ ✓ ✓ P5CHATEN3 – – ✓ P5CHATEN2 – – ✓ P5CHATEN1 ✓ ✓ ✓ P5CHATEN0 ✓ ✓ ✓ Seiko Epson Corporation 7-24 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 106: P6 Port Group
7–6 – – – – – – P6IN5 – ✓ ✓ ✓ P6IN4 ✓ ✓ ✓ P6IN3 ✓ ✓ ✓ P6IN2 ✓ ✓ ✓ P6IN1 ✓ ✓ ✓ P6IN0 ✓ ✓ ✓ Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 7-25 (Rev. 1.1)
Page 107 – – – Filter Enable Register) P6CHATEN5 – ✓ ✓ ✓ P6CHATEN4 ✓ ✓ ✓ P6CHATEN3 ✓ ✓ ✓ P6CHATEN2 ✓ ✓ ✓ P6CHATEN1 ✓ ✓ ✓ P6CHATEN0 ✓ ✓ ✓ Seiko Epson Corporation 7-26 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 108: Pd Port Group
✓ ✓ ✓ PDIEN0 ✓ ✓ ✓ 7–4 – – – – – – PDOEN3 – ✓ ✓ ✓ PDOEN2 ✓ ✓ ✓ PDOEN1 ✓ ✓ ✓ PDOEN0 ✓ ✓ ✓ Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 7-27 (Rev. 1.1)
Page 109: Common Registers Between Port Groups
Group Register) – P6INT ✓ ✓ ✓ P5INT ✓ ✓ ✓ P4INT ✓ ✓ ✓ P3INT ✓ ✓ ✓ P2INT ✓ ✓ ✓ P1INT ✓ ✓ ✓ P0INT – ✓ ✓ Seiko Epson Corporation 7-28 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 110: Universal Port Multiplexer (Upmux)
4. Initialize the peripheral circuit. 5. Set the PPORTPxFNCSEL.PxyMUX[1:0] bits of the I/O port to 0x1. (Select peripheral I/O function 1) 6. Set the PPORTPxMODSEL.PxSELy bit of the I/O port to 1. (Enable peripheral I/O function) Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 111: Control Registers
Note: Do not assign a peripheral input function to two or more I/O ports. Although the I/O ports output the same waveforms when an output function is assigned to two or more I/O port, a skew oc- curs due to the internal delay. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 112: Watchdog Timer (Wdt2)
CLK_WDT2 supply is suspended, the register retains the status before DEBUG mode was entered. If the WDT2CLK.DBRUN bit = 1, the CLK_WDT2 supply is not suspended and WDT2 will keep operating in DEBUG mode. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 113: Operations
1. Write 0x0096 to the SYSPROT.PROT[15:0] bits. (Remove system protection) 2. Write 0xa to the WDT2CTL.WDTRUN[3:0] bits. (Stop WDT2) 3. Write a value other than 0x0096 to the SYSPROT.PROT[15:0] bits. (Set system protection) Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 114: Operations In Halt And Sleep Modes
IOSC OSC1 OSC3 EXOSC 1/65,536 1/128 1/65,536 1/32,768 1/32,768 1/16,384 1/16,384 1/8,192 1/8,192 (Note) The oscillation circuits/external input that are not supported in this IC cannot be selected as the clock source. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 115: Wdt2 Control Register
WDT2 should also be reset concurrently when running WDT2. WDT2 Counter Compare Match Register Register name Bit name Initial Reset Remarks WDT2CMP 15–10 – 0x00 – – 9–0 CMP[9:0] 0x3ff R/WP Bits 15–10 Reserved Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 116 These bits set the NMI/reset generation cycle. The value set in this register is compared with the 10-bit counter value while WDT2 is running, and an NMI or reset is generated when they are matched. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 117: Real-Time Clock (Rtca)
* Indicates the status when the pin is configured for RTCA. If the port is shared with the RTCA output function and other functions, the RTCA function must be assigned to the port. For more information, refer to the “I/O Ports” chapter. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 10-1...
Page 118: Clock Settings
· · · · · · · · · · · · 0x3e 59.1 0x7e -1.9 0x3f 60.1 0x7f -1.0 Minimum resolution: 1 ppm, Correction rate range: -61.0 to 60.1 ppm Seiko Epson Corporation 10-2 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 119: Operations
3. Write 1 to the RTCAINTF.ALARMIF bit to clear the alarm interrupt flag. 4. Write 1 to the RTCAINTE.ALARMIE bit to enable alarm interrupts. When the real-time clock counter reaches the alarm time set in Step 2, an alarm interrupt occurs. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 10-3...
Page 120: Real-Time Clock Counter Operations
10.4.4 Stopwatch Count-up Pattern The stopwatch consists of 1/100-second and 1/10-second counters and these counters perform counting up in incre- ments of approximate 1/100 and 1/10 seconds with the count-up patterns shown in Figure 10.4.4.1. Seiko Epson Corporation 10-4 S1C31D41 TECHNICAL MANUAL...
Page 121: Interrupts
1 Hz counter value. • An alarm interrupt occurs after a lapse of 1/256 second from matching between the AM/PM (in 12H mode), hour, minute, and second counter value and the alarm setting value. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 10-5...
Page 122: Control Registers
This bit executes the 30-second correction time adjustment function. 1 (W): Execute 30-second correction 0 (W): Ineffective 1 (R): 30-second correction is executing. 0 (R): 30-second correction has finished. (Normal operation) Seiko Epson Corporation 10-6 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 123: Rtca Control Register (High Byte)
1 as well. However, no correcting operation is performed. RTCA Second Alarm Register Register name Bit name Initial Reset Remarks RTCAALM1 – – – 14–12 RTCSHA[2:0] 11–8 RTCSLA[3:0] 7–0 – 0x00 – Bit 15 Reserved Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 10-7 (Rev. 1.1)
Page 124: Rtca Hour/Minute Alarm Register
BCD code. RTCA Stopwatch Control Register Register name Bit name Initial Reset Remarks RTCASWCTL 15–12 BCD10[3:0] – 11–8 BCD100[3:0] 7–5 – – SWRST Read as 0. 3–1 – – – SWRUN Seiko Epson Corporation 10-8 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 125: Rtca Second/1Hz Register
10-second digit and the 1-second digit of the second counter, respectively. The setting/read values are a BCD code within the range from 0 to 59. Note: Be sure to avoid writing to the RTCASEC.RTCSH[2:0]/RTCSL[3:0] bits while the RTCACTLL. RTCBSY bit = 1. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 10-9 (Rev. 1.1)
Page 126: Rtca Hour/Minute Register
1 to 12 in 12H mode or 0 to 23 in 24H mode. Note: Be sure to avoid writing to the RTCAHUR.RTCHH[1:0]/RTCHL[3:0] bits while the RTCACTLL. RTCBSY bit = 1. Bit 7 Reserved Seiko Epson Corporation 10-10 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 127: Rtca Month/Day Register
These bits are used to set and read day of the week. The day of the week counter is a base-7 counter and the setting/read values are 0x0 to 0x6. Table 10.6.2 lists the correspondence between the count value and day of the week. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 10-11...
Page 128: Rtca Interrupt Flag Register
The following shows the correspondence between the bit and interrupt: RTCAINTF.RTCTRMIF bit: Theoretical regulation completion interrupt RTCAINTF.SW1IF bit: Stopwatch 1 Hz interrupt RTCAINTF.SW10IF bit: Stopwatch 10 Hz interrupt RTCAINTF.SW100IF bit: Stopwatch 100 Hz interrupt Bits 11–9 Reserved Seiko Epson Corporation 10-12 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 129: Rtca Interrupt Enable Register
The following shows the correspondence between the bit and interrupt: RTCAINTE.RTCTRMIE bit: Theoretical regulation completion interrupt RTCAINTE.SW1IE bit: Stopwatch 1 Hz interrupt RTCAINTE.SW10IE bit: Stopwatch 10 Hz interrupt RTCAINTE.SW100IE bit: Stopwatch 100 Hz interrupt Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 10-13 (Rev. 1.1)
Page 130 RTCAINTE.T1DAYIE bit: 1-day interrupt RTCAINTE.T1HURIE bit: 1-hour interrupt RTCAINTE.T1MINIE bit: 1-minute interrupt RTCAINTE.T1SECIE bit: 1-second interrupt RTCAINTE.T1_2SECIE bit: 1/2-second interrupt RTCAINTE.T1_4SECIE bit: 1/4-second interrupt RTCAINTE.T1_8SECIE bit: 1/8-second interrupt RTCAINTE.T1_32SECIE bit: 1/32-second interrupt Seiko Epson Corporation 10-14 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 131: Supply Voltage Detector (Svd3)
EXSVD0 EXSEL External voltage selector Voltage SVDDT EXSVD1 comparator circuit VDSEL Detection SVDSC[1:0] SVDIF result counter SVDIE SVDRE[3:0] Interrupt/reset To system reset circuit control circuit To CPU Figure 11.1.1 SVD3 Configuration Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 11-1 (Rev. 1.1)
Page 132: Input Pins And External Connection
If the CLGOSC.xxxxSLPC bit for the CLK_SVD3 clock source is 1, the CLK_SVD3 clock source is deactivated during SLEEP mode and SVD3 stops with the register settings maintained at those before entering SLEEP mode. After the CPU returns to normal mode, CLK_SVD3 is supplied and the SVD3 operation resumes. Seiko Epson Corporation 11-2 S1C31D41 TECHNICAL MANUAL...
Page 133: Clock Supply In Debug Mode
SVD3CTL.MODEN bit = 1, wait for at least SVD circuit response SVD_EXT time before reading the SVD3INTF.SVDDT bit (refer to “Supply Voltage Detector Characteristics, SVD circuit response time t ” in the “Electrical Characteristics” chapter). Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 11-3 (Rev. 1.1)
Page 134: Svd3 Operations
SVDIF bit). An interrupt request is sent to the CPU only when the SVD3INTF.SVDIF bit is set while the interrupt is enabled by the SVD3INTE.SVDIE bit. For more information on interrupt control, refer to the “Interrupt” chapter. Seiko Epson Corporation 11-4 S1C31D41 TECHNICAL MANUAL (Rev.
Page 135: Svd3 Reset
Bit 7 Reserved Bits 6–4 CLKDIV[2:0] These bits select the division ratio of the SVD3 operating clock. Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the clock source of SVD3. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 11-5 (Rev. 1.1)
Page 136: Svd3 Control Register
0x01 ↓ 0x00 For the configurable range and voltage values, refer to “Supply Voltage Detector Characteristics, SVD detection voltage V /EXSVD detection voltage V ” in the “Electrical Characteristics” chapter. SVD_EXT Seiko Epson Corporation 11-6 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 137: Svd3 Status And Interrupt Flag Register
, EXSVDn) < SVD detection voltage V or EXSVD detection voltage V SVD_EXT 0 (R): Power supply voltage (V , EXSVDn) ≥ SVD detection voltage V or EXSVD detection voltage V SVD_EXT Bits 7–1 Reserved Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 11-7 (Rev. 1.1)
Page 138: Svd3 Interrupt Enable Register
• To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared before enabling interrupts. Seiko Epson Corporation 11-8 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 139: 16-Bit Timers (T16)
If the port is shared with the EXCLm pin and other functions, the EXCLm input function must be assigned to the port before using the event counter function. The EXCLm signal can be input through the chattering filter. For more information, refer to the “I/O Ports” chapter. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 12-1...
Page 140: Clock Settings
(Set reload data (counter preset data)) 5. Set the following bits when using the interrupt: - Write 1 to the T16_nINTF.UFIF bit. (Clear interrupt flag) - Set the T16_nINTE.UFIE bit to 1. (Enable underflow interrupt) Seiko Epson Corporation 12-2 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 141: Counter Underflow
At the same time the counter stops, the T16_ nCTL.PRUN bit is cleared automatically. Select this mode to stop the counter after an interrupt has occurred once, such as for checking a specific lapse of time. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 12-3...
Page 142: Counter Value Read
Bits 7–4 CLKDIV[3:0] These bits select the division ratio of the T16 Ch.n operating clock (counter clock). Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the clock source of T16 Ch.n. Seiko Epson Corporation 12-4 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 143: T16 Ch.n Control Register
PRESET MODEN Bits 15–9 Reserved Bit 8 PRUN This bit starts/stops the timer. 1 (W): Start timer 0 (W): Stop timer 1 (R): Timer is running 0 (R): Timer is idle Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 12-5 (Rev. 1.1)
Page 144: T16 Ch.n Reload Data Register
This bit indicates the T16 Ch.n underflow interrupt cause occurrence status. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective Seiko Epson Corporation 12-6 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 145: T16 Ch.n Interrupt Enable Register
This bit enables T16 Ch.n underflow interrupts. 1 (R/W): Enable interrupts 0 (R/W): Disable interrupts Note: To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared before enabling interrupts. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 12-7 (Rev. 1.1)
Page 146: Uart (Uart3)
CRPER[7:0] OUTMD TENDIE TENDIF FEIE FEIF Interrupt PEIE PEIF control circuit OEIE OEIF RB2FIE RB2FIF RB1FIE RB1FIF TBEIE TBEIF DMA request TBEDMAENx RB1FDMAENx control circuit DMA controller Figure 13.1.1 UART3 Configuration Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 13-1 (Rev. 1.1)
Page 147: Input/Output Pins And External Connections
(Clock source selection) - UART3_nCLK.CLKDIV[1:0] bits (Clock division ratio selection = Clock frequency setting) The UART3 operating clock should be selected so that the baud rate generator will be configured easily. Seiko Epson Corporation 13-2 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 148: Clock Supply In Sleep Mode
(UART3_nMOD.STPB bit = 1). Parity function The parity function is configured using the UART3_nMOD.PREN and UART3_nMOD.PRMD bits. Table 13.4.1 Parity Function Setting UART3_nMOD.PREN bit UART3_nMOD.PRMD bit Parity function Odd parity Even parity Non parity Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 13-3 (Rev. 1.1)
Page 149: Operations
8. Configure the DMA controller and set the following UART3 control bits when using DMA transfer: - Write 1 to the DMA transfer request enable bits in the UART3_nTBEDMAEN and UART3_nRB1FDMAEN registers. (Enable DMA transfer requests) Seiko Epson Corporation 13-4 S1C31D41 TECHNICAL MANUAL...
Page 150: Data Transmission
Read the UART3_nINTF.TBEIF bit UART3_nINTF.TBEIF = 1 ? Write transmit data to the UART3_nTXD register Transmit data remained? Wait for an interrupt request (UART3_nINTF.TBEIF = 1) Figure 13.5.2.2 Data Transmission Flowchart Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 13-5 (Rev. 1.1)
Page 151: Data Reception
UART3_nINTF.RB1FIF bit to 1 (receive buffer one byte full). If the sec- ond data is received without reading the first data, the UART3_nINTF.RB2FIF bit is set to 1 (receive buffer two bytes full). Seiko Epson Corporation 13-6 S1C31D41 TECHNICAL MANUAL...
Page 152: Irda Interface
Set the UART3_nMOD.IRMD bit to 1 to use the IrDA interface. Data transfer control is identical to that for normal interface even if the IrDA interface function is enabled. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 13-7...
Page 153: Carrier Modulation
CAREN = 0 CAREN = 1 USOUTn PECAR = 0 (INVTX = 1) CAREN = 1 PECAR = 1 Figure 13.5.5.1 Carrier Modulation Waveform (UART3_nMOD.CHLN = 1, UART3_nMOD.STPB = 0, UART3_nMOD.PREN = 1) Seiko Epson Corporation 13-8 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 154: Receive Errors
When an overrun error occurs, the UART3_nINTF.OEIF bit (overrun error interrupt flag) is set to 1. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 13-9 (Rev.
Page 155: Interrupts
After a DMA transfer has completed, disable the DMA transfer to prevent unintended DMA transfer requests from being issued. For more information on the DMA control, refer to the “DMA Controller” chapter. Seiko Epson Corporation 13-10 S1C31D41 TECHNICAL MANUAL...
Page 156: Control Registers
UART3 Ch.n Mode Register Register name Bit name Initial Reset Remarks UART3_nMOD 15–13 – – – PECAR CAREN BRDIV INVRX INVTX – – PUEN OUTMD IRMD CHLN PREN PRMD STPB Bits 15–13 Reserved Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 13-11 (Rev. 1.1)
Page 157 1 (R/W): Enable parity function 0 (R/W): Disable parity function Bit 1 PRMD This bit selects either odd parity or even parity when using the parity function. 1 (R/W): Odd parity 0 (R/W): Even parity Seiko Epson Corporation 13-12 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 158: Uart3 Ch.n Baud-Rate Register
Note: If the UART3_nCTL.MODEN bit is altered from 1 to 0 while sending/receiving data, the data being sent/received cannot be guaranteed. When setting the UART3_nCTL.MODEN bit to 1 again after that, be sure to write 1 to the UART3_nCTL.SFTRST bit as well. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 13-13...
Page 159: Uart3 Ch.n Transmit Data Register
This bit indicates the receiving status. (See Figure 13.5.3.1.) 1 (R): During receiving 0 (R): Idle Bit 8 TBSY This bit indicates the sending status. (See Figure 13.5.2.1.) 1 (R): During sending 0 (R): Idle Bit 7 Reserved Seiko Epson Corporation 13-14 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 160: Uart3 Ch.n Interrupt Enable Register
UART3_nINTE.PEIE bit: Parity error interrupt UART3_nINTE.OEIE bit: Overrun error interrupt UART3_nINTE.RB2FIE bit: Receive buffer two bytes full interrupt UART3_nINTE.RB1FIE bit: Receive buffer one byte full interrupt UART3_nINTE.TBEIE bit: Transmit buffer empty interrupt Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 13-15 (Rev. 1.1)
Page 161: Uart3 Ch.n Transmit Buffer Empty Dma Request Enable Register
UART3_nCAWF 15–8 – 0x00 – – 7–0 CRPER[7:0] 0x00 Bits 15–8 Reserved Bits 7–0 CRPER[7:0] These bits set the carrier modulation output frequency. For more information, refer to “Carrier Modu- lation.” Seiko Epson Corporation 13-16 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 162: Synchronous Serial Interface (Spia)
CPOL Pull-up/down control PUEN circuit (Used only in slave mode) #SPISSn Interrupt TENDIE TENDIF control circuit RBFIE RBFIF TBEIE TBEIF DMA request controller RBFDMAENx control circuit TBEDMAENx Figure 14.1.1 SPIA Configuration Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 14-1 (Rev. 1.1)
Page 163: Input/Output Pins And External Connections
SDIn #SPISS0 SPICLKn #SPISS1 #SPISS #SPISS2 External SPI master device External SPI slave devices SPICLK SPICLK #SPISS SPICLK Figure 14.2.2.2 Connections between SPIA in Slave Mode and External SPI Master Device Seiko Epson Corporation 14-2 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 164: Pin Functions In Master Mode And Slave Mode
16-bit timer channel and converts it to the SPICLKn. The 16-bit timer must be run with an appro- priate reload data set. The SPICLKn frequency (baud rate) and the 16-bit timer reload data are calculated by the equations shown below. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 14-3...
Page 165: Clock Supply During Debugging
SDIn SDOn (Master mode) SDOn (Slave mode) SDOn (Slave mode) Writing data to the SPIA_nTXD register Figure 14.3.3.1 SPI Clock Phase and Polarity (SPIA_nMOD.LSBFST bit = 0, SPIA_nMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation 14-4 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 166: Data Format
6. Configure the DMA controller and set the following SPIA control bits when using DMA transfer: - Write 1 to the DMA transfer request enable bits in the SPIA_nTBEDMAEN and SPIA_nRBFDMAEN registers. (Enable DMA transfer requests) Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 14-5...
Page 167: Data Transmission In Master Mode
Data (W) → SPIA_nTXD Data (W) → SPIA_nTXD Software operations Data (W) → SPIA_nTXD 1 (W) → SPIA_nINTF.TENDIF Figure 14.5.2.1 Example of Data Sending Operations in Master Mode (SPIA_nMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation 14-6 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 168 Transfer destination SPIA_nTXD register address Control data dst_inc 0x3 (no increment) dst_size 0x1 (haflword) src_inc 0x1 (+2) src_size 0x1 (halfword) R_power 0x0 (arbitrated for every transfer) n_minus_1 Number of transfer data cycle_ctrl 0x1 (basic transfer) Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 14-7 (Rev. 1.1)
Page 169: Data Reception In Master Mode
Software operations SPIA_nRXD → Data (R) Data (W) → SPIA_nTXD SPIA_nRXD → Data (R) 1 (W) → SPIA_nINTF.TENDIF Figure 14.5.3.1 Example of Data Receiving Operations in Master Mode (SPIA_nMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation 14-8 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 170 Control data dst_inc 0x3 (no increment) dst_size 0x1 (haflword) src_inc 0x3 (no increment) src_size 0x1 (halfword) R_power 0x0 (arbitrated for every transfer) n_minus_1 Number of transfer data cycle_ctrl 0x1 (basic transfer) Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 14-9 (Rev. 1.1)
Page 171: Terminating Data Transfer In Master Mode
• Slave mode starts data transfer when SPICLKn is input from the external SPI master after the #SPISSn signal is asserted. Writing transmit data is not a trigger to start data transfer. Therefore, it is not necessary to write dummy data to the transmit data buffer when performing data reception only. Seiko Epson Corporation 14-10 S1C31D41 TECHNICAL MANUAL...
Page 172: Terminating Data Transfer In Slave Mode
1. Wait for an end-of-transmission interrupt (SPIA_nINTF.TENDIF bit = 1). Or determine end of transfer via the received data. 2. Set the SPIA_nCTL.MODEN bit to 0 to disable the SPIA Ch.n operations. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 14-11 (Rev. 1.1)
Page 173: Interrupts
SPIA_nINTF.BSY SPIA_nMOD register CPOL bit CPHA bit SPICLKn SDOn SPICLKn SDOn SPIA_nINTF.TENDIF Writing data to the SPIA_nTXD register Figure 14.6.1 SPIA_nINTF.BSY and SPIA_nINTF.TENDIF Bit Set Timings (when SPIA_nMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation 14-12 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 174: Dma Transfer Requests
16 bits 15 bits 14 bits 13 bits 12 bits 11 bits 10 bits 9 bits 8 bits 7 bits 6 bits 5 bits 4 bits 3 bits 2 bits Setting prohibited Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 14-13 (Rev. 1.1)
Page 175: Spia Ch.n Control Register
Note: If the SPIA_nCTL.MODEN bit is altered from 1 to 0 while sending/receiving data, the data being sent/received cannot be guaranteed. When setting the SPIA_nCTL.MODEN bit to 1 again after that, be sure to write 1 to the SPIA_nCTL.SFTRST bit as well. Seiko Epson Corporation 14-14 S1C31D41 TECHNICAL MANUAL...
Page 176: Spia Ch.n Transmit Data Register
These bits indicate the SPIA interrupt cause occurrence status. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag (OEIF, TENDIF) 0 (W): Ineffective Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 14-15 (Rev. 1.1)
Page 177: Spia Ch.n Interrupt Enable Register
Ch.15) when a receive buffer full state has occurred. 1 (R/W): Enable DMA transfer request 0 (R/W): Disable DMA transfer request Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented chan- nels are ineffective. Seiko Epson Corporation 14-16 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 178: Quad Synchronous Serial Interface (Qspi)
48-pin package 64-pin package Number of channels 1 channels (Ch.0) Internal clock input Ch.0 ← 16-bit timer Ch.2 Memory mapped access area 1M-byte area beginning with address 0x0004_0000 for external Flash memory Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 15-1 (Rev. 1.1)
Page 179: Input/Output Pins And External Connections
In this case, GPIO pins other than #QSPISSn can also be used as the slave select output ports to connect the QSPI to more than one external QSPI device. Figures 15.2.2.1 to 15.2.2.7 show connection diagrams between the QSPI in each mode and external QSPI devices. Seiko Epson Corporation 15-2 S1C31D41 TECHNICAL MANUAL...
Page 180 External dual-I/O SPI slave devices QSDIOn0 SDIO0 QSPICLKn SPICK #SPISS SDIO1 SDIO0 SPICK Figure 15.2.2.3 Connections between QSPI in Register Access Master Mode and External Dual-I/O SPI Slave Devices Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 15-3 (Rev. 1.1)
Page 181 #SPISS2 External single-I/O SPI master device SPICK SPICK External single-I/O SPI slave devices #SPISS SPICK Figure 15.2.2.5 Connections between QSPI in Slave Mode and External Single-I/O SPI (Legacy SPI) Master Device Seiko Epson Corporation 15-4 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 182 QSDIO2 QSDIO2 QSDIO1 QSDIO1 QSDIO0 QSDIO0 QSPICLK QSPICLK External QSPI slave devices #QSPISS QSDIO3 QSDIO2 QSDIO1 QSDIO0 QSPICLK Figure 15.2.2.7 Connections between QSPI in Slave Mode and External QSPI Master Device Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 15-5 (Rev. 1.1)
Page 183: Pin Functions In Master Mode And Slave Mode
To supply CLK_QSPIn to the QSPI, the 16-bit timer clock source must be enabled in the clock generator. It does not matter how the T16_mCTL.MODEN and T16_mCTL.PRUN bits of the corresponding 16-bit timer channel are set (1 or 0). Seiko Epson Corporation 15-6 S1C31D41 TECHNICAL MANUAL...
Page 184: Clock Supply During Debugging
(Master mode, output) QSDIOn (Slave mode, output) QSDIOn (Slave mode, output) QSDIOn Writing data to the QSPI_nTXD register Figure 15.3.3.1 QSPI Clock Phase and Polarity (QSPI_nMOD.LSBFST bit = 0, QSPI_nMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 15-7 (Rev. 1.1)
Page 185: Data Format
Figure 15.4.2 Data Format Selection for Dual Transfer Mode Using the QSPI_nMOD.LSBFST Bit (QSPI_nMOD.TMOD[1:0] bits = 0x1, QSPI_nMOD.CHDL[3:0] bits = 0x7, QSPI_nMOD.CHLN[3:0] bits = 0x7, QSPI_nMOD.CPOL bit = 0, QSPI_nMOD.CPHA bit = 0) Seiko Epson Corporation 15-8 S1C31D41 TECHNICAL MANUAL...
Page 186: Operations
(QSPI_nCTL.DIR bit = 1). The number of data transfer clocks is configured with the QSPI_nMOD. CHLN[3:0] bits. Since four data lines are used for data transfer, the data bit length (number of clocks) is obtained by dividing the number of transfer data bits by four. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 15-9...
Page 187: Memory Mapped Access Mode
The QSPI treats the data cycle as 2 cycles including 2 driving cycles. (QSPI_nMOD.CHDL[3:0] bits = 0x1, QSPI_nMOD.CHLN[3:0] bits = 0x1) Figure 15.5.2.1 XIP Example - Spansion S25FL128S Quad I/O Read Command Sequence (3-byte address, 0xeb [ExtAdd = 0], LC = 0b00) Seiko Epson Corporation 15-10 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 188: Initialization
- QSPI_nMOD.NOCLKDIV bit (Select master mode operating clock) - QSPI_nMOD.LSBFST bit (Select MSB first/LSB first) - QSPI_nMOD.CPHA bit (Select clock phase) - QSPI_nMOD.CPOL bit (Select clock polarity) - QSPI_nMOD.MST bit (Select master/slave mode) Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 15-11 (Rev. 1.1)
Page 189: Data Transmission In Master Mode
Even if the clock is being output from the QSPICLKn pin, the next transmit data can be written to the QSPI_ nTXD register after making sure the QSPI_nINTF.TBEIF bit is set to 1. Seiko Epson Corporation 15-12 S1C31D41 TECHNICAL MANUAL...
Page 190 DMA transfer in advance so that transmit data will be transferred to the QSPI_nTXD register. For more information on DMA, refer to the “DMA Controller” chapter. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 15-13...
Page 191: Data Reception In Register Access Master Mode
TMOD[1:0] bits is received when the QSPI_nINTF.RBFIF bit is set to 1, the QSPI_nRXD register is overwritten with the newly received data and the previously received data is lost. In this case, the QSPI_nINTF.OEIF bit is set. Seiko Epson Corporation 15-14 S1C31D41 TECHNICAL MANUAL...
Page 192 DMA controller and dummy data is transferred from the specified memory to the QSPI_ nTXD register via DMA Ch.x when the QSPI_nINTF.TBEIF bit is set to 1 (transmit buffer empty). Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 15-15...
Page 193 DMA controller transfers data from the QSPI_nRXD register and then writes another dummy byte to the QSPI_nTXD register, allowing the QSPI to read the next data. 13. Wait for a DMA interrupt. Seiko Epson Corporation 15-16 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 194: Data Reception In Memory Mapped Access Mode
If the address in the memory mapped access area that is continuous to the previous read address is read when the FIFO contains the prefetched data (FIFO data ready status), the prefetched data is sent to the internal system bus with the HREADY signal held high (zero-wait read). Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 15-17...
Page 195 Data cycle 3 QSPI_nMOD register Dummy cycle Data cycle 1 (prefetching) (prefetching) CPOL bit CPHA bit QSPICLKn QSDIOn[3:0] Figure 15.5.6.1 Data Receiving Operation in Memory Mapped Access Mode - First 32-bit Read Seiko Epson Corporation 15-18 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 196 HRDATA fifo_read_level Data cycle Data cycle QSPI_nMOD register (for n+8) (prefetching) CPOL bit CPHA bit QSPICLKn QSDIOn[3:0] Figure 15.5.6.2 Data Receiving Operation in Memory Mapped Access Mode - 32-bit Sequential Read Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 15-19 (Rev. 1.1)
Page 197 Dummy cycle (low-order 16 bits) (for n) (for n+8) QSPI_nMOD register #QSPISSn CPOL bit CPHA bit QSPICLKn QSDIOn[3:0] Figure 15.5.6.3 Data Receiving Operation in Memory Mapped Access Mode - 32-bit Non-Sequential Read Seiko Epson Corporation 15-20 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 198 HADDR HTRANS HSIZE HREADY HRDATA QSPI_nMOD register Dummy cycle Data cycle CPOL bit CPHA bit QSPICLKn QSDIOn[3:0] Figure 15.5.6.4 Data Receiving Operation in Memory Mapped Access Mode - First 8/16-bit Read Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 15-21 (Rev. 1.1)
Page 199 HCLK HSEL HADDR HTRANS HSIZE HREADY HRDATA QSPI_nMOD register Data cycle CPOL bit CPHA bit QSPICLKn QSDIOn[3:0] Figure 15.5.6.5 Data Receiving Operation in Memory Mapped Access Mode - 8/16-bit Sequential Read Seiko Epson Corporation 15-22 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 200 Address cycle Dummy cycle Data cycle (low-order 16 bits) QSPI_nMOD register #QSPISSn CPOL bit CPHA bit QSPICLKn QSDIOn[3:0] Figure 15.5.6.6 Data Receiving Operation in Memory Mapped Access Mode - 8/16-bit Non-Sequential Read Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 15-23 (Rev. 1.1)
Page 201 The transfer source/destination and control data must be set for the DMA controller and the relevant DMA channel must be enabled to start a DMA transfer in advance. For more information on DMA, refer to the “DMA Controller” chapter. Seiko Epson Corporation 15-24 S1C31D41 TECHNICAL MANUAL...
Page 202: Terminating Memory Mapped Access Operations
1. Wait for an end-of-transmission interrupt (QSPI_nINTF.TENDIF bit = 1). 2. Set the QSPI_nCTL.MODEN bit to 0 to disable the QSPI Ch.n operations. 3. Stop the 16-bit timer to disable the clock supply to QSPI Ch.n. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 15-25...
Page 203: Data Transfer In Slave Mode
Data (W) → QSPI_nTXD Software operations QSPI_nRXD → Data (R) QSPI_nRXD → Data (R) Figure 15.5.9.1 Example of Data Transfer Operations in Slave Mode (QSPI_nMOD.CHDL[3:0] bits = QSPI_nMOD.CHLN[3:0] bits = 0x3) Seiko Epson Corporation 15-26 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 204: Terminating Data Transfer In Slave Mode
The QSPI_nINTF register also contains the BSY and MMABSY bits that indicate the QSPI operating status in reg- ister access and memory mapped access modes, respectively. Figure 15.6.1 shows the QSPI_nINTF.BSY, QSPI_ nINTF.MMABSY and QSPI_nINTF.TENDIF bit set timings. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 15-27...
Page 205: Dma Transfer Requests
When a 32-bit data is prefetched into the FIFO When the FIFO read access FIFO data FIFO data ready flag in memory mapped access mode level is cleared to 0 ready (internal signal) Seiko Epson Corporation 15-28 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 206: Control Registers
Note: When using the QSPI in slave mode, the QSPI_nMOD.CHDL[3:0] bits should be set to the same value as the QSPI_nMOD.CHLN[3:0] bits. Bits 11–8 CHLN[3:0] These bits set the number of clocks for data transfer. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 15-29 (Rev. 1.1)
Page 207 0 (R/W): MSB first Bit 2 CPHA Bit 1 CPOL These bits set the QSPI clock phase and polarity. For more information, refer to “QSPI Clock (QSPI- CLKn) Phase and Polarity.” Seiko Epson Corporation 15-30 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 208: Qspi Ch.n Control Register
Note: If the QSPI_nCTL.MODEN bit is altered from 1 to 0 while sending/receiving data, the data being sent/received cannot be guaranteed. When setting the QSPI_nCTL.MODEN bit to 1 again after that, be sure to write 1 to the QSPI_nCTL.SFTRST bit as well. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 15-31...
Page 209: Qspi Ch.n Transmit Data Register
Transmit/receive busy 0 (R): Idle Bit 6 MMABSY This bit indicates the QSPI memory mapped access operating status. 1 (R): Memory mapped access state machine busy 0 (R): Idle Bits 5–4 Reserved Seiko Epson Corporation 15-32 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 210: Qspi Ch.n Interrupt Enable Register
Ch.15) when a transmit buffer empty state has occurred. 1 (R/W): Enable DMA transfer request 0 (R/W): Disable DMA transfer request Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented chan- nels are ineffective. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 15-33 (Rev. 1.1)
Page 211: Qspi Ch.n Receive Buffer Full Dma Request Enable Register
11 clocks 10 clocks 9 clocks 8 clocks 7 clocks 6 clocks 5 clocks 4 clocks 3 clocks 2 clocks 1 clock Note: These bits specify a number of system clocks. Seiko Epson Corporation 15-34 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 212: Qspi Ch.n Remapping Start Address High Register
Flash memory in the memory mapped access mode. This setting is re- quired to output the XIP confirmation bit to Micron Flash memories or to output the mode byte to Spansion Flash memories. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 15-35...
Page 213 The QSDIOn[3:0] pins are used. Dual transfer mode The QSDIOn[1:0] pins are used. The QSDIOn[3:2] pins are not used. Single transfer mode The QSDIOn[1:0] pins are used. The QSDIOn[3:2] pins are not used. Seiko Epson Corporation 15-36 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 214: Qspi Ch.n Mode Byte Register
Note: In memory mapped access mode, the mode byte is always output from the LSB first. When us- ing a Flash memory that expects the mode byte to be output from the MSB first, write the mode byte to this register in reverse bit order. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 15-37...
Page 215: C (I2C)
OADR10 OADR[9:0] Slave mode GCEN controller SDALOW SCLLOW TXNACK TXSTART Master mode TXSTOP controller SCLn CLKSRC[1:0] CLKDIV[1:0] Clock DBRUN Baud rate SCLO generator MODEN BRT[6:0] generator CLK_I2Cn Figure 16.1.1 I2C Configuration Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 16-1 (Rev. 1.1)
Page 216: Input/Output Pins And External Connections
• The internal pull-up resistors for the I/O ports cannot be used for pulling up SDA and SCL. • When the I2C is set into master mode, no other master device can be connected to the I bus. Seiko Epson Corporation 16-2 S1C31D41 TECHNICAL MANUAL...
Page 217: Clock Settings
16.3.3.1). Note: The I C bus transfer rate is limited to 100 kbit/s in standard mode or 400 kbit/s in fast mode. Do not set a transfer rate exceeding the limit. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 16-3 (Rev. 1.1)
Page 218: Operations
- Set the I2C_nCTL.MST bit to 0. (Set slave mode) - Set the I2C_nCTL.SFTRST bit to 1. (Execute software reset) - Set the I2C_nCTL.MODEN bit to 1. (Enable I2C Ch.n operations) Seiko Epson Corporation 16-4 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 219: Data Transmission In Master Mode
I2C_nINTF.NACKIF bit = 1 (NACK received), the I2C Ch.n generates a repeated START condi- tion. When the repeated START condition has been generated, the I2C_nINTF.STARTIF and I2C_nINTF. TBEIF bits are both set to 1 same as when a START condition has been generated. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 16-5...
Page 220 Last data sent? Retry? Write 1 to the I2C_nCTL.TXSTOP bit Write data to the I2C_nTXD register Wait for an interrupt request (I2C_nINTF.STOPIF = 1) Figure 16.4.2.2 Master Mode Data Transmission Flowchart Seiko Epson Corporation 16-6 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 221: Data Reception In Master Mode
10. (When DMA is not used) Repeat Steps 6 to 8 until the end of data reception. 11. Wait for a STOP condition interrupt (I2C_nINTF.STOPIF bit = 1). Clear the I2C_nINTF.STOPIF bit by writing 1 after the interrupt has occurred. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 16-7...
Page 222 S: START condition, Sr: Repeated START condition, P: STOP condition, A: ACK, A: NACK, Saddr/R: Slave address + R(1), Data n: 8-bit data Figure 16.4.3.1 Example of Data Receiving Operations in Master Mode Seiko Epson Corporation 16-8 S1C31D41 TECHNICAL MANUAL...
Page 223 Transfer destination Memory address to which the last received data is stored Control data dst_inc 0x0 (+1) dst_size 0x0 (byte) src_inc 0x3 (no increment) src_size 0x0 (byte) R_power 0x0 (arbitrated for every transfer) n_minus_1 Number of receive data cycle_ctrl 0x1 (basic transfer) Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 16-9 (Rev. 1.1)
Page 224: 10-Bit Addressing In Master Mode
Clear the I2C_nINTF.STARTIF bit by writing 1 after the interrupt has occurred. 9. Write the first address to the I2C_nTXD.TXD[7:1] bits and 1 that represents READ as the data transfer di- rection to the I2C_nTXD.TXD0 bit. 10. Perform data reception. Seiko Epson Corporation 16-10 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 225: Data Transmission In Slave Mode
Go to Step 6 when a STOP condition interrupt has occurred. ii. Go to Step 2 when a START condition interrupt has occurred. 6. Clear the I2C_nINTF.STOPIF bit and then terminate data sending operations. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 16-11...
Page 226 A: ACK, A: NACK, Saddr/R: Slave address + R(1), Saddr/W: Slave address + W(0), STARTIF = 1 Data n: 8-bit data Figure 16.4.5.1 Example of Data Sending Operations in Slave Mode Seiko Epson Corporation 16-12 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 227: Data Reception In Slave Mode
I2C Ch.n sends an ACK and pulls down SCL to low. The received data in the shift register is transferred to the receive data buffer and the I2C_nINTF.RBFIF and I2C_nINTF.BYTEENDIF bits are both set to 1. After that, the received data can be read out from the I2C_nRXD register. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 16-13...
Page 228 Wait for an interrupt request (I2C_nINTF.RBFIF = 1) Last data received next? Write 1 to the I2C_nCTL.TXNACK bit Read receive data from the I2C_nRXD register Last data received? Figure 16.4.6.2 Slave Mode Data Reception Flowchart Seiko Epson Corporation 16-14 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 229: Slave Operations In 10-Bit Address Mode
If SDA does not change from low when the I2C Ch.n outputs the ninth clock, it is regarded as an automatic bus clearing failure. In this case, the I2C Ch.n clears the I2C_nCTL.TXSTART bit to 0 and sets both the I2C_nINTF. ERRIF and I2C_nINTF.STARTIF bits to 1. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 16-15...
Page 230: Error Detection
4 <Master mode only> When 1 is written to the I2C_nCTL. I2C_nINTF.ERRIF = 1 TXSTART bit while the I2C_nINTF.BSY bit = 0 (Refer to “Au- Automatic bus clearing I2C_nCTL.TXSTART = 0 tomatic Bus Clearing Operation.”) failure I2C_nINTF.STARTIF = 1 Seiko Epson Corporation 16-16 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 231: Interrupts
Master mode BRT + 3 CLK_I2Cn TXSTART = 1 TXSTART = 0 STARTIF = 1 Slave mode Address matching the I2C_nOADR register BSY = 1 TR = 0/1 STARTIF = 1 Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 16-17 (Rev. 1.1)
Page 232: Dma Transfer Requests
16.7 Control Registers I2C Ch.n Clock Control Register Register name Bit name Initial Reset Remarks I2C_nCLK 15–9 – 0x00 – – DBRUN 7–6 – – 5–4 CLKDIV[1:0] 3–2 – – 1–0 CLKSRC[1:0] Seiko Epson Corporation 16-18 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 233: I2C Ch.n Mode Register
Note: The I2C_nMOD register settings can be altered only when the I2C_nCTL.MODEN bit = 0. I2C Ch.n Baud-Rate Register Register name Bit name Initial Reset Remarks I2C_nBR 15–8 – 0x00 – – – – 6–0 BRT[6:0] 0x7f Bits 15–7 Reserved Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 16-19 (Rev. 1.1)
Page 234: I2C Ch.n Own Address Register
STOP condition has been generated. This bit is automatically cleared when the bus free time (t defined in the I C Specifications) has elapsed after the STOP condition has been generated. Seiko Epson Corporation 16-20 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 235: I2C Ch.n Transmit Data Register
Register name Bit name Initial Reset Remarks I2C_nRXD 15–8 – 0x00 – – 7–0 RXD[7:0] 0x00 Bits 15–8 Reserved Bits 7–0 RXD[7:0] The receive data buffer can be read through these bits. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 16-21 (Rev. 1.1)
Page 236: I2C Ch.n Status And Interrupt Flag Register
Bit 0 TBEIF These bits indicate the I2C interrupt cause occurrence status. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective Seiko Epson Corporation 16-22 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 237: I2C Ch.n Interrupt Enable Register
I2C_nINTE.NACKIE bit: NACK reception interrupt I2C_nINTE.STOPIE bit: STOP condition interrupt I2C_nINTE.STARTIE bit: START condition interrupt I2C_nINTE.ERRIE bit: Error detection interrupt I2C_nINTE.RBFIE bit: Receive buffer full interrupt I2C_nINTE.TBEIE bit: Transmit buffer empty interrupt Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 16-23 (Rev. 1.1)
Page 238: I2C Ch.n Transmit Buffer Empty Dma Request Enable Register
(Ch.0–Ch.15) when a receive buffer full state has occurred. 1 (R/W): Enable DMA transfer request 0 (R/W): Disable DMA transfer request Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented chan- nels are ineffective. Seiko Epson Corporation 16-24 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 239: 16-Bit Pwm Timers (T16B)
Ch.1: CAP10 to CAP13 pin inputs (4 systems) Note: In this chapter, ‘n’ refers to a channel number, and ‘m’ refers to an input/output pin number or a comparator/capture circuit number in a channel. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 17-1...
Page 240: Input/Output Pins
If the port is shared with the T16B pin and other functions, the T16B input/output function must be assigned to the port before activating T16B. For more information, refer to the “I/O Ports” chapter. Seiko Epson Corporation 17-2 S1C31D41 TECHNICAL MANUAL...
Page 241: Clock Settings
Figure 17.3.4.1 Count Timing (During Count Up Operation) Note: When running the counter using the event counter clock, two dummy clocks must be input be- fore the first counting up/down can be performed. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 17-3...
Page 242: Operations
5. Set the following bits when using the interrupt: - Write 1 to the interrupt flags in the T16B_nINTF register. (Clear interrupt flags) - Set the interrupt enable bits in the T16B_nINTE register to 1. (Enable interrupts) Seiko Epson Corporation 17-4 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 243: Counter Block Operations
T16Bn, one of the operations shown below is required to read correctly by the CPU. - Read the counter value twice or more and check to see if the same value is read. - Stop the timer and then read the counter value. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 17-5...
Page 244 0x0000 and continues counting down from the new MAX value after a counter under- flow occurs. In one-shot down count mode, the counter returns to the MAX value if a counter underflow occurs and stops automatically at that point. Seiko Epson Corporation 17-6 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 245 0x0000 and then starts counting up to the new MAX val- In one-shot up/down count mode, the counter stops automatically when it reaches 0x0000 during count down operation. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 17-7...
Page 246: Comparator/Capture Block Operations
When the counter reaches the MAX value in comparator mode, the T16B_nINTF.CNTMAXIF bit (counter MAX interrupt flag) is set to 1. When the counter reaches 0x0000, the T16B_nINTF.CNTZEROIF bit (counter zero interrupt flag) is set to 1. Seiko Epson Corporation 17-8 S1C31D41 TECHNICAL MANUAL...
Page 247 Count cycle = — — — — — — — — [s] (Eq. 17.2) CLK_T16B CLK_T16B Where T16B_nCCRm register setting value (0 to 65,535) MAX: T16B_nMC register setting value (0 to 65,535) : Count clock frequency [Hz] CLK_T16B Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 17-9 (Rev. 1.1)
Page 248 (T16B_nMC register) Compare period Compare buffer Counter value Time 0x0000 CNTMAXIF = 1 CNTMAXIF = 1 CNTMAXIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation 17-10 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 249 Count cycle MAX value (T16B_nMC register) Compare period Compare buffer Counter value Time 0x0000 CNTMAXIF = 1 CNTMAXIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 17-11 (Rev. 1.1)
Page 250 Compare buffer value Compare period Time 0x0000 CNTZEROIF = 1 CNTZEROIF = 1 CNTZEROIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation 17-12 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 251 Time 0x0000 CNTMAXIF = 1 CNTZEROIF = 1 CNTMAXIF = 1 CNTZEROIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 17-13 (Rev. 1.1)
Page 252 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 (Note that the T16B_nINTF.CMPCAPmIF/CNTMAXIF/CNTZEROIF bit clearing operations via software are omitted from the figure.) Figure 17.4.3.2 Compare Buffer Operations Seiko Epson Corporation 17-14 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 253 If the captured data stored in the T16B_nCCRm register is overwritten by the next trigger when the T16B_ nINTF.CMPCAPmIF bit is still set, an overwrite error occurs (the T16B_nINTF.CAPOWmIF bit is set). Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 17-15...
Page 254 Capture trigger signal T16B_nCCRm.CC[15:0] Capturing operation (2) Asynchronous capture mode (When T16B_nCCCTLm.CAPTRG[1:0] bits = 0x3) Count clock T16B_nTC.TC[15:0] Capture trigger signal T16B_nCCRm.CC[15:0] Capturing operation Figure 17.4.3.4 Synchronous Capture Mode/Asynchronous Capture Mode Seiko Epson Corporation 17-16 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 255: Tout Output Control
Furthermore, when the T16B_nCCCTLm.TOUTMT bit is set to 1, the TOUT circuit uses the MATCH signal output from another system in the circuit pair (0 and 1, 2 and 3, 4 and 5). This makes it possible to change the signal twice within a counter cycle. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 17-17...
Page 256 Software control mode (0x0) Set mode (0x1) Toggle/reset mode (0x2) Set/reset mode (0x3) Toggle mode(0x4) Reset mode (0x5) Toggle/set mode (0x6) Reset/set mode (0x7) ∗ ( ) indicates the T16B_nCCCTLm.TOUTMD[2:0] bit-setting value. Seiko Epson Corporation 17-18 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 257 Set/reset mode (0x3) Toggle mode(0x4) Reset mode (0x5) Toggle/set mode (0x6) Reset/set mode (0x7) ∗ ( ) indicates the T16B_nCCCTLm.TOUTMD[2:0] bit-setting value. Figure 17.4.4.2 TOUT Output Waveform (T16B_nCCCTLm.TOUTMT bit = 0) Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 17-19 (Rev. 1.1)
Page 258 Set/reset mode (0x3) TOUTn0 TOUTn1 Toggle mode(0x4) TOUTn0 TOUTn1 Reset mode (0x5) TOUTn0 TOUTn1 Toggle/set mode (0x6) TOUTn0 TOUTn1 Reset/set mode (0x7) TOUTn0 TOUTn1 ∗ ( ) indicates the T16B_nCCCTLm.TOUTMD[2:0] bit-setting value. Seiko Epson Corporation 17-20 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 259 Set/reset mode (0x3) TOUTn0 TOUTn1 Toggle mode(0x4) TOUTn0 TOUTn1 Reset mode (0x5) TOUTn0 TOUTn1 Toggle/set mode (0x6) TOUTn0 TOUTn1 Reset/set mode (0x7) TOUTn0 TOUTn1 ∗ ( ) indicates the T16B_nCCCTLm.TOUTMD[2:0] bit-setting value. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 17-21 (Rev. 1.1)
Page 260 Toggle/set mode (0x6) TOUTn0 TOUTn1 Reset/set mode (0x7) TOUTn0 TOUTn1 ∗ ( ) indicates the T16B_nCCCTLm.TOUTMD[2:0] bit-setting value. Figure 17.4.4.3 TOUT Output Waveform (T16B_nCCCTL0.TOUTMT bit = 1, T16B_nCCCTL1.TOUTMT bit = 0) Seiko Epson Corporation 17-22 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 261: Interrupt
Bit 8 DBRUN This bit sets whether the T16B Ch.n operating clock is supplied during debugging or not. 1 (R/W): Clock supplied during debugging 0 (R/W): No clock supplied during debugging Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 17-23 (Rev. 1.1)
Page 262 T16B_nCTL.ONEST bit setting (see Table 17.7.2). Bit 3 ONEST This bit selects the counter repeat/one-shot mode. The count mode is configured with this selection and the T16B_nCTL.CNTMD[1:0] bit settings (see Table 17.7.2). Seiko Epson Corporation 17-24 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 263: T16B Ch.n Max Counter Data Register
T16B_nCTL.MODEN bit to 1 until the T16B_nCS.BSY bit is set to 0 from 1. • Do not set the T16B_nMC.MC[15:0] bits to 0x0000. T16B Ch.n Timer Counter Data Register Register name Bit name Initial Reset Remarks T16B_nTC 15–0 TC[15:0] 0x0000 – Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 17-25 (Rev. 1.1)
Page 264: T16B Ch.n Counter Status Register
This bit indicates the currently set count direction. 1 (R): Count up 0 (R): Count down Bit 0 This bit indicates the counter operating status. 1 (R): Running 0 (R): Idle Seiko Epson Corporation 17-26 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 265: T16B Ch.n Interrupt Flag Register
Note: The configuration of the T16B_nINTF.CAPOWmIF and T16B_nINTF.CMPCAPmIF bits depends on the model. The bits corresponding to the comparator/capture circuits that do not exist are read-only bits and are always fixed at 0. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 17-27...
Page 266: T16B Ch.n Interrupt Enable Register
The bits corresponding to the comparator/capture circuits that do not exist are read-only bits and are always fixed at 0. • To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared before enabling interrupts. Seiko Epson Corporation 17-28 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 267: T16B Ch.n Comparator/Capture M Control Register
These bits select the trigger edge(s) of the trigger signal at which the counter value is captured in the T16B_nCCRm register in capture mode (see Table 17.7.4). The T16B_nCCCTLm.CAPTRG[1:0] bits are control bits for capture mode and are ineffective in comparator mode. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 17-29...
Page 268 T h e s i g n a l b e c o m e s i n a c t i v e b y t h e M AT C H m o r MATCHm+1 signal. TOUTnm+1 The signal becomes inactive by the MATCHm+1 or MATCHm signal. Seiko Epson Corporation 17-30 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 269: T16B Ch.n Compare/Capture M Data Register
In capture mode, this register is configured as the capture register and the counter value captured by the capture trigger signal is loaded. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 17-31 (Rev. 1.1)
Page 270: T16B Ch.n Counter Max/Zero Dma Request Enable Register
(Ch.0–Ch.15) when the counter value reaches the compare data or is captured. 1 (R/W): Enable DMA transfer request 0 (R/W): Disable DMA transfer request Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented chan- nels are ineffective. Seiko Epson Corporation 17-32 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 271: Ir Remote Controller (Remc3)
Function REMO O (L) IR remote controller transmit data output CLPLS O (L) IR remote controller clear pulse output * Indicates the status when the pin is configured for the REMC3. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 18-1 (Rev. 1.1)
Page 272: External Connections
1. Write 1 to the REMC3DBCTL.REMCRST bit. (Reset REMC3) 2. Configure the REMC3CLK.CLKSRC[1:0] and REMC3CLK.CLKDIV[3:0] bits. (Configure operating clock) 3. Assign the REMC3 output function to the port. (Refer to the “I/O Ports” chapter.) Seiko Epson Corporation 18-2 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 273: Data Transmission Procedures
The REMC3 outputs the logical AND between the carrier signal output from the carrier generator and the data sig- nal output from the data signal generator. Figure 18.4.3.1 shows an example of the output waveform. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 18-3 (Rev.
Page 274 The data signal is generated by comparing the values of the 16-bit counter for data signal generation (REMC3DBCNT.DBCNT[15:0] bits) that runs with CLK_REMC3 and the setting values of the REMC3A- PLEN.APLEN[15:0] and REMC3DBLEN.DBLEN[15:0] bits. Figure 18.4.3.3 shows an example of the data signal generated. Seiko Epson Corporation 18-4 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 275: Continuous Data Transmission And Compare Buffers
(REMC3DBCTL.TRMD bit = 1), the counter stops automatically when the counter value is matched with the REMC3DBLEN.DBLEN[15:0] bit-setting value. 18.4.4 Continuous Data Transmission and Compare Buffers Figure 18.4.4.1 shows an operation example of continuous data transmission with the compare buffer enabled. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 18-5 (Rev. 1.1)
Page 276: Interrupts
The REMC3 provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the CPU only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For more information on interrupt control, refer to the “Interrupt” chapter. Seiko Epson Corporation 18-6 S1C31D41 TECHNICAL MANUAL...
Page 277: Application Example: Driving El Lamp
This bit sets whether the REMC3 operating clock is supplied during debugging or not. 1 (R/W): Clock supplied during debugging 0 (R/W): No clock supplied during debugging Bits 7–4 CLKDIV[3:0] These bits select the division ratio of the REMC3 operating clock. Bits 3–2 Reserved Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 18-7 (Rev. 1.1)
Page 278: Remc3 Data Bit Counter Control Register
This bit starts/stops counting by the internal counters (16-bit counter for data signal generation and 8-bit counter for carrier generation). 1 (W): Start counting 0 (W): Stop counting 1 (R): Counting 0 (R): Idle Seiko Epson Corporation 18-8 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 279: Remc3 Data Bit Counter Register
0x0000 H0/S0 Cleared by writing 1 to the REMC3DBCTL.REMCRST bit. Bits 15–0 DBCNT[15:0] The current value of the 16-bit counter for data signal generation can be read out through these bits. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 18-9 (Rev. 1.1)
Page 280: Remc3 Data Bit Active Pulse Length Register
Transfer to the REMC3APLEN buffer has not completed. 0 (R): Transfer to the REMC3APLEN buffer has completed. While this bit is set to 1, writing to the REMC3APLEN.APLEN[15:0] bits is ineffective. Seiko Epson Corporation 18-10 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 281: Remc3 Interrupt Enable Register
REMC3CARR.CRPER[7:0] bit-setting value. (See Figure 18.4.3.2.) REMC3 Carrier Modulation Control Register Register name Bit name Initial Reset Remarks REMC3CCTL 15–9 – 0x00 – – OUTINVEN 7–1 – 0x00 – CARREN Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 18-11 (Rev. 1.1)
Page 282 This bit enables carrier modulation. 1 (R/W): Enable carrier modulation 0 (R/W): Disable carrier modulation (output data signal only) Note: When carrier modulation is disabled, the REMC3DBCTL.REMOINV bit should be set to 0. Seiko Epson Corporation 18-12 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 283: 12-Bit A/D Converter (Adc12A)
Figure 19.1.1 ADC12A Configuration Note: In this chapter, n, m, and k refer to an ADC12A channel number, an analog input pin number, and a 16-bit timer channel number, respectively. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 19-1 (Rev. 1.1)
Page 284: Input Pins And External Connections
: acquisition time). Figure 19.3.2.1 shows an equivalent circuit of the analog input portion. ADINnm ADIN ADIN Source impedance : Analog input resistance ADIN : Analog input capacitance ADIN Figure 19.3.2.1 Equivalent Circuit of Analog Input Portion Seiko Epson Corporation 19-2 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 285: Operations
Writing 1 to the ADC12A_nCTL.ADST bit enables the ADC12A to accept trigger inputs. After that, A/D con- version is started when an underflow occurs in the 16-bit timer Ch.k. Software trigger Writing 1 to the ADC12A_nCTL.ADST bit starts A/D conversion. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 19-3 (Rev. 1.1)
Page 286: Conversion Mode And Analog Input Pin Settings
3. Read the A/D conversion result of the analog input m (ADC12A_nADD.ADD[15:0] bits). 4. Repeat Steps 2 and 3 until terminating A/D conversion. 5. Write 0 to the ADC12A_nCTL.ADST bit. The ADC12A stops operating after the A/D conversion currently being executed has completed. Seiko Epson Corporation 19-4 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 287 The transfer source/destination and control data must be set for the DMA controller and the relevant DMA channel must be enabled to start a DMA transfer in advance. For more information on DMA, refer to the “DMA Controller” chapter. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 19-5...
Page 288: Interrupts
After a DMA transfer has completed, disable the DMA transfer to prevent unintended DMA transfer requests from being issued. For more information on the DMA control, refer to the “DMA Controller” chapter. Seiko Epson Corporation 19-6 S1C31D41 TECHNICAL MANUAL...
Page 289: Control Registers
Note: The data written to the ADC12A_nCTL.ADST bit must be retained for one or more CLK_T16_ k clock cycles when 1 is written or two or more CLK_T16_k clock cycles when 0 is written. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 19-7 (Rev.
Page 290: Adc12A Ch.n Trigger/Analog Input Select Register
Right justified (ADC12A_nTRG.STMD bit = 0) 0 (MSB) 12-bit conversion result (LSB) Figure 19.7.1 Conversion Data Alignment Bit 6 CNVMD This bit sets the A/D conversion mode. 1 (R/W): Continuous conversion mode 0 (R/W): One-time conversion mode Seiko Epson Corporation 19-8 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 291: Adc12A Ch.n Configuration Register
A/D conversion. • Be aware that ADC circuit current I flows if the ADC12_nCFG.VRANGE[1:0] bits are set to a value other than 0x0 when the ADC12_nCTL.BSYSTAT bit = 1. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 19-9 (Rev. 1.1)
Page 292: Adc12A Ch.n Interrupt Flag Register
0 (R/W): Disable interrupts The following shows the correspondence between the bit and interrupt: ADC12A_nINTE.OVIE bit: A/D conversion result overwrite error interrupt ADC12A_nINTE.ADmCIE bit: Analog input signal m A/D conversion completion interrupt Seiko Epson Corporation 19-10 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 293: Adc12A Ch.n Dma Request Enable Register M
ADC12A Ch.n Result Register Register name Bit name Initial Reset Remarks ADC12A_nADD 15–0 ADD[15:0] 0x0000 – Bits 15–0 ADD[15:0] The A/D conversion results are set to these bits. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 19-11 (Rev. 1.1)
Page 294: Temperature Sensor/Reference Voltage Generator (Tsrvr)
If the port is shared with the TSRVR pin and other functions, the TSRVR output function must be assigned to the port before activating the TSRVR. For more information, refer to the “I/O Ports” chapter. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 20-1 (Rev.
Page 295: External Connections
ADD: A/D conversion result at temperature T or T (decimal) : A/D converter reference voltage [V] REFA For details of the internal A/D converter, refer to the “12-bit A/D Converter” chapter. Seiko Epson Corporation 20-2 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 296: Control Registers
TSRVR_nVCTL.VREFAMD[1:0] VREFA bits are set to 0x2 or 0x3. • When the TSRVR_nVCTL.VREFAMD[1:0] bits are not set to 0x0, do not apply an external voltage to the VREFAm pin. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 20-3 (Rev. 1.1)
Page 297: F Converter (Rfc)
Time base counter DBRUN TC[23:0] MODEN Counter RFCLKOn control circuit Measurement counter MC[23:0] CONEN SSENB RFINn EVTEN CR oscillation SSENA Oscillation REFn SMODE[1:0] control circuit SREF circuit SENAn SENBn Figure 21.1.1 RFC Configuration Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 21-1 (Rev. 1.1)
Page 298: Input/Output Pins And External Connections
Figure 21.2.2.1 Connection Example in Resistive Sensor DC Oscillation Mode SENBn SEN1 SENAn REFn RFINn : Reference resistor : Resistive sensor (AC bias) SEN1 S1C31 RFC : Reference capacitor Figure 21.2.2.2 Connection Example in Resistive Sensor AC Oscillation Mode Seiko Epson Corporation 21-2 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 299: Clock Settings
(Clear interrupt flags) - Set the interrupt enable bits in the RFC_nINTE register to 1. (Enable interrupts) 3. Assign the RFC input/output function to the ports. (Refer to the “I/O Ports” chapter.) Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 21-3 (Rev. 1.1)
Page 300: Operating Modes
To obtain the difference between the reference oscillation and sensor oscillation clock count values from the measurement counter simply, appropriate initial values must be set to the measurement counter before starting reference oscillation. Seiko Epson Corporation 21-4 S1C31D41 TECHNICAL MANUAL...
Page 301: Converting Operations And Control Procedure
The measurement counter overflow sets the RFC_nINTF.EREFIF bit to 1 indicating that the reference os- cillation has been terminated normally. If the RFC_nINTE.EREFIE bit = 1, a reference oscillation comple- tion interrupt request occurs at this point. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 21-5...
Page 302 Performing reference oscillation and sensor oscillation with the same resistor and capacitor results n ≈ m. The difference between n and m is a conversion error. Table 21.4.4.1 lists the error factors. (n: measurement counter initial value, m: measurement counter value at the end of sensor oscillation) Seiko Epson Corporation 21-6 S1C31D41 TECHNICAL MANUAL...
Page 303: Cr Oscillation Frequency Monitoring Function
The RFC provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the CPU only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For more infor- mation on interrupt control, refer to the “Interrupt” chapter. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 21-7...
Page 304: Control Registers
This bit sets the RFCLKOn pin to output the divided-by-two oscillation clock. 1 (R/W): Divided-by-two clock output 0 (R/W): Oscillation clock output For more information, refer to “CR Oscillation Frequency Monitoring Function.” Seiko Epson Corporation 21-8 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 305: Rfc Ch.n Oscillation Trigger Register
This bit controls CR oscillation for sensor A. This bit also indicates the CR oscillation status. 1 (W): Start oscillation 0 (W): Stop oscillation 1 (R): Being oscillated 0 (R): Stopped Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 21-9 (Rev. 1.1)
Page 306: Rfc Ch.n Measurement Counter Low And High Registers
Note: The time base counter must be set from the low-order value (RFC_nTCL.TC[15:0] bits) first when data is set using a 16-bit access instruction. The counter may not be set to the correct value if the high-order value (RFC_nTCH.TC[23:16] bits) is written first. Seiko Epson Corporation 21-10 S1C31D41 TECHNICAL MANUAL...
Page 307: Rfc Ch.n Interrupt Flag Register
RFC_nINTE.OVTCIE bit: Time base counter overflow error interrupt RFC_nINTE.OVMCIE bit: Measurement counter overflow error interrupt RFC_nINTE.ESENBIE bit: Sensor B oscillation completion interrupt RFC_nINTE.ESENAIE bit: Sensor A oscillation completion interrupt RFC_nINTE.EREFIE bit: Reference oscillation completion interrupt Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 21-11 (Rev. 1.1)
Page 308: Hw Processor (Hwp) And Sound Output (Sdac2)
The fea- tures of the HWP are listed below. Sound Play function • EPSON high quality and high compression algorithm (EOV: EPSON Original Sound Format) - Sampling Frequency: 15.625 kHz - Bitrate: 16/24 kbps •...
Page 309: Output Pins And External Connections
SDAC2 positive sound signal 2 output (dedicated for four-pin output mode) SDACOUT_N2 O O (L) SDAC2 negative sound signal 2 output (dedicated for four-pin output mode) * Indicates the status when the pin is configured for SDAC2. Seiko Epson Corporation 22-2 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 310 Enable SDACOUT_N 39 nF 39 nF Audio amplifier SDACOUT_P 39 nF 39 nF S1C31 SDAC Low-pass filter (Cutoff: 8 kHz) * SDAC2MOD.PWMMODE[1:0] bits = 0x1 Figure 22.2.2.2 Differential Mode Connection Example Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 22-3 (Rev. 1.1)
Page 311: Hwp Operating Clock
The SYSCLK supply to the SDAC2 during DEBUG mode can be controlled using the SDAC2CLK.DBRUN bit. The SDAC2CLK.DBRUN bit must be set to 1 when using the Sound Play function during DEBUG mode. Be aware that the sound cannot be output normally when SDAC2CLK.DBRUN bit = 0. Seiko Epson Corporation 22-4 S1C31D41 TECHNICAL MANUAL...
Page 312: Operations
- INTMASK.TO_IDLE bit (Set idle state interrupt mask) - ROMADDR.ADDRESS[31:0] bits (Set sound ROM data start address) - ROMSIZE.SIZE[31:0] bits (Set sound ROM data size) - KEYCODE.KEYCODE[31:0] bits (Set key code) Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 22-5 (Rev. 1.1)
Page 313 This is a standby state in which the Sound Play function stops playback output. This state allows issuance of the Sound Start command. After the Sound Start command is issued, the HWP transits to sp_state_play state to start playback output. Seiko Epson Corporation 22-6 S1C31D41 TECHNICAL MANUAL...
Page 314 Single channel playback output start procedure The following shows a Ch.n playback output start procedure: 1. Confirm that the STATE_n.STATE[15:0] bits = 0x0001 (sp_state_idle). 2. Confirm that the STATUS.READY bit = 1. (Command acceptable) Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 22-7 (Rev. 1.1)
Page 315 (Select Sound Start command) - SENTENCE_0.SENTENCE_NO[15:0] bits (Specify sentence number) - VOLUME_0.VOLUME[15:0] bits (Specify volume level) - REPEAT_0.REPEAT[15:0] bits (Specify repeat count) - SPEED_0.SPEED[15:0] bits (Specify playback speed) - PITCH_0.PITCH[15:0] bits (Specify playback pitch) Seiko Epson Corporation 22-8 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 316 (fade-out) process for the playback output signal is carried out to suppress the occurrence of noise. Sound level Smoothing process Time Command execution (Mute/Pause/Stop Immediately command) Figure 22.4.1.2 Smoothing Process when Playback Output is Suspended Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 22-9 (Rev. 1.1)
Page 317 7. Write 0 to the HWPINTF.HWP0IF bit. (Clear interrupt flag) * Two pause commands are available. Setting the COMMAND_n.COMMAND[7:0] bits to 0x04 selects the Pause Immediately command; setting to 0x05 selects the Pause after Current Phrase command. Seiko Epson Corporation 22-10 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 318 (See Figure 22.4.1.3.) In the pause or mute state, the playback is terminated by releasing the pause or mute state immediately re- gardless of which of the Sound Stop commands is issued. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 22-11 (Rev. 1.1)
Page 319 3. Set the SDAC2CTL.TONEON bit to 1. (Start tone signal (square wave) output) Output is in progress. Terminating output 4. Set the SDAC2CTL.TONEON bit to 0. (Stop tone signal (square wave) output) Seiko Epson Corporation 22-12 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 320: Memory Check Function
_ram_rw _ram_march_c _checksum _crc Figure 22.4.2.1 Memory check State Transition Diagram As shown in the figure above, there are seven operating states in the Memory Check function. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 22-13 (Rev. 1.1)
Page 321 2. Confirm that the STATUS.READY bit = 1. (Command acceptable) 3. Set the COMMAND.COMMAND[7:0] bits. (Select command) 4. Set the MEMADDR.ADDRESS[31:0] bits. (Specify check start address) 5. Set the MEMSIZE.SIZE[31:0] bits. (Specify check size (byte)) Seiko Epson Corporation 22-14 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 322 When this command is issued by the trigger bit, the HWP transits to mc_state_ram_march_c state to ex- ecute the RAM marching test (March-C algorithm). Note: When an error occurs during RAM check, the check is terminated at the address where the error has occurred. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 22-15 (Rev. 1.1)
Page 323 Note: The HWP uses memory mapped access mode (refer to the “Quad Synchronous Serial Interface” chapter) for the external QSPI-Flash check. Therefore, external Flash memories that do not sup- port XIP (eXecute-In-Place) cannot be checked. Seiko Epson Corporation 22-16 S1C31D41 TECHNICAL MANUAL...
Page 324: External Qspi Flash Memory Access
1. Before disabling the HWP, set the mode byte for terminating the XIP session to the QSPI_nMB.XI- PEXT[7:0] bits. 2. Disable the HWP. 3. Perform the procedure described in Section 15.5.7. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 22-17 (Rev. 1.1)
Page 325: Interrupts
STATUS Operating Status Register STATUS Operating Status Register Base + 0x48 – – RESULT Calculation Result Register Base + 0x4c VERSION Version Number Register VERSION Version Number Register Base = 0x00156700 Seiko Epson Corporation 22-18 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 326: Sound Play Function Registers
These bits specify the sound data ROM start address. The address should be specified with a value shown below. In case of internal Flash: 0x00 0000, …, 0x02 fff0 (16-byte alignment) Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 22-19 (Rev. 1.1)
Page 327: Rom Size Register
Reset Remarks KEYCODE 31–0 KEYCODE[31:0] – – (Sound Play) Bits 31–0 KEYCODE[31:0] These bits specify the key code. Write the key code provided by Seiko Epson. Ch.n Command Register Register name Bit name Initial Reset Remarks COMMAND_n 15–8 OPTION[7:0] –...
Page 328: N Sentence Number Setting Register
0x00 Silent Ch.n Repeat Control Register Register name Bit name Initial Reset Remarks REPEAT_n 15–0 REPEAT[15:0] – – (Sound Play) Bits 15–0 REPEAT[15:0] These bits specify the number of repeat playbacks. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 22-21 (Rev. 1.1)
Page 329: 0 Playback Speed Conversion Register
Standard speed 0x5f 0x5a 0x55 0x50 ↓ 0x4b Slow Other Setting prohibited Ch.0 Playback Pitch Conversion Register Register name Bit name Initial Reset Remarks PITCH_0 15–0 PITCH[15:0] – – (Sound Play) Seiko Epson Corporation 22-22 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 330: N State Monitor Register
Ch.n State Monitor Register Register name Bit name Initial Reset Remarks STATE_n 15–0 STATE[15:0] – – (Sound Play) Bits 15–0 STATE[15:0] These bits indicate the current state of the Sound Play function. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 22-23 (Rev. 1.1)
Page 331: Error Status Register
Bit name Initial Reset Remarks VERSION 15–8 MAJOR[7:0] – – 7–0 MINOR[7:0] – Bits 15–8 MAJOR[7:0] Bits 7–0 MINOR[7:0] These bits indicate the HWP version number. Version number = MAJOR[7:0] . MINOR[7:0] Seiko Epson Corporation 22-24 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 332: Memory Check Function Register
0x00 0000 + OFFSET, …, 0x0f ffff + OFFSET * The OFFSET is 0x04 0000, the start address of the memory mapped access area for external Flash memory (refer to “Figure 4.1.1 Memory Map”). Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 22-25...
Page 333: Memory Size Register
Bits 15–0 STATE[15:0] These bits indicate the current state of the Memory Check function. Table 22.6.2.2 State Monitor STATE.STATE[15:0] bits State 0x0005 mc_state_crc 0x0004 mc_state_checksum 0x0003 mc_state_ram_march_c 0x0002 mc_state_ram_rw 0x0001 mc_state_idle 0x0000 mc_state_init Seiko Epson Corporation 22-26 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 334: Error Status Register
Bit name Initial Reset Remarks VERSION 15–8 MAJOR[7:0] – – 7–0 MINOR[7:0] – Bits 15–8 MAJOR[7:0] Bits 7–0 MINOR[7:0] These bits indicate the HWP version number. Version number = MAJOR[7:0] . MINOR[7:0] Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 22-27 (Rev. 1.1)
Page 335: Control Registers
1 (R/W): Enable interrupts 0 (R/W): Disable interrupts HWP Command Trigger Register Register name Bit name Initial Reset Remarks HWPCMDTRG 15–8 – 0x00 – – 7–1 – 0x00 – HWP0TRG Bits 15–1 Reserved Seiko Epson Corporation 22-28 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 336: Sdac2 Clock Control Register
– TONEON – – RESAMPEN SDACEN Bits 15–4 Reserved Bit 3 TONEON This bit enables the square-wave tone generator. 1 (R/W): Turn on square-wave tone 0 (R/W): Turn off square-wave tone Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 22-29 (Rev. 1.1)
Page 337: Sdac2 Mode Register
SDAC2 Interrupt Flag Register Register name Bit name Initial Reset Remarks SDAC2INTF 15–8 – 0x00 – – 7–4 – – ERR1IF Cleared by writing 1. DATREQ1IF ERR0IF DATREQ0IF Bits 15–4 Reserved Seiko Epson Corporation 22-30 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 338: Sdac2 Interrupt Enable Register
Note: This register is used by the HWP. Do not write any data to this register while the HWP operation is enabled (HWPCTL.HWPEN bit = 1). SDAC2 Resampler Rate Register Register name Bit name Initial Reset Remarks SDAC2RESAMP 15–11 – 0x00 – – 10–0 RESAMPRATE[10:0] 0x400 Bits 15–11 Reserved Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 22-31 (Rev. 1.1)
Page 339: Sdac2 Tone Divider Register
/ [(4 × TONEDIV + 4) × 2] (Eq. 22.2) SDAC2CLK where : SDAC2 operating clock frequency set using the SDAC2CLK register [Hz] SDAC2CLK TONEDIV: Value set in the SDAC2TONE.TONEDIV[15:0] bits Seiko Epson Corporation 22-32 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 340: Electrical Characteristics
*3 R are not required when using the debug pins as general-purpose I/O ports. DBG1–2 *4 The component values should be determined after evaluating operations using an actual mounting board. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 23-1 (Rev. 1.1)
Page 341: Current Consumption
*3 OSC1 oscillator: CLGOSC1.OSC1SELCR bit = 0, CLGOSC1.INV1N[1:0] bits = 0x0, CLGOSC1.CGI1[2:0] bits = 0x0, CLGOSC1. OSDEN bit = 0, C = 0 pF, Crystal resonator = C-002RX (manufactured by Seiko Epson Corporation, R = 50 kW (Max.), = 7 pF) *4 OSC1 oscillator: CLGOSC1.OSC1SELCR bit = 1...
Page 342 Ta [°C] Current consumption-temperature characteristic in HALT mode (OSC3 operation) IOSC =OFF, OSC1 = 32.768 kHz, OSC3 = ON (internal oscillator), Typ. value 16 MHz 8 MHz 4 MHz Ta [°C] Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 23-3 (Rev. 1.1)
Page 343 IOSC = OFF, OSC1 = 32.768 kHz, OSC3 = ON (internal oscillator), Typ. value 3,500 16 MHz 3,000 CLGOSC1.OSC1SELCR bit = 1 2,500 2,000 8 MHz 1,500 4 MHz 1,000 Ta [°C] Ta [°C] Seiko Epson Corporation 23-4 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 344: System Reset Controller (Src) Characteristics
= 0 V, Ta = -40 to 85°C Item Symbol Condition Min. Typ. Max. Unit – Reset hold time RSTR *1 Time until the internal reset signal is negated after the reset request is canceled. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 23-5 (Rev. 1.1)
Page 345 = 1.8 to 5.5 V, PWGACTL.REGSEL bit = 1, Typ. value = 1.8 to 5.5 V, PWGACTL.REGSEL bit = 0, Typ. value CLGIOSC.IOSCFQ[1:0] bits = 0x1 CLGIOSC.IOSCFQ[1:0] bits = 0x2 Ta [°C] Ta [°C] Seiko Epson Corporation 23-6 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 346 CLGOSC1.OSC1SELCR bit = 1 31.04 32.96 OSC1I oscillation frequency *1 CLGOSC1.CGI1[2:0] bits = 0x0, Crystal resonator = C-002RX (manufactured by Seiko Epson Corporation, R = 50 kW (Max.), C = 7 pF) OSC1 internal oscillation frequency-temperature characteristic Typ. value Ta [°C]...
Page 347: Flash Memory Characteristics
Flash is being programmed, as it affects the Flash memory characteristics (programming count). *2 Assumed that Erasing + Programming as count of 1. The count includes programming in the factory for shipment with ROM data programmed. Seiko Epson Corporation 23-8 S1C31D41 TECHNICAL MANUAL...
Page 348: Input/Output Port (Pport) Characteristics
Ta = 85°C, Min. value –V = 5.5 V = 3.6 V = 1.8 V = 1.8 V = 3.6 V = 5.5 V 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 23-9 (Rev. 1.1)
Page 349 4.61 SVD3CTL.SVDC[4:0] bits = 0x1b 4.49 4.72 SVD3CTL.SVDC[4:0] bits = 0x1c 4.58 4.82 SVD3CTL.SVDC[4:0] bits = 0x1d 4.68 4.92 SVD3CTL.SVDC[4:0] bits = 0x1e 4.78 5.02 SVD3CTL.SVDC[4:0] bits = 0x1f 4.88 5.13 Seiko Epson Corporation 23-10 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 350 *1 If CLK_SVD3 is configured in the neighborhood of 32 kHz, the SVD3INTF.SVDDT bit is masked during the t period and it SVDEN retains the previous value. CLK_SVD3 SVD3CTL.MODEN 0x1e 0x10 SVD3CTL.SVDC[4:0] SVD3INTF.SVDDT Invalid Valid Invalid Valid SVDEN Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 23-11 (Rev. 1.1)
Page 351: Uart (Uart3) Characteristics
1.8 to 3.6 V mode1 – – SDO0 output delay time = 15 pF 1.8 to 5.5 V mode0 – – 1.8 to 3.6 V mode1 – – *1 C = Pin load Seiko Epson Corporation 23-12 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 352 (CPOL, CPHA) = (1, 0) or (0, 1) SPICLKn (CPOL, CPHA) = (1, 1) or (0, 0) SDIn SDOn Slave mode #SPISSn SPICLKn (CPOL, CPHA) = (0, 1) SPICLKn (CPOL, CPHA) = (1, 0) SDIn Hi-Z SDOn Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 23-13 (Rev. 1.1)
Page 353: Quad Synchronous Serial Interface (Qspi) Characteristics
– – STOP condition setup time t – – – – µs SU:STO – – Bus free time – – µs * After this period, the first clock pulse is generated. Seiko Epson Corporation 23-14 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 354: 12-Bit A/D Converter (Adc12A) Characteristics
, ADIN = V /2, f = 100 ksps, Ta = 25°C, Typ. value REFA REFA 1,100 ADC12A_nCFG.VRANGE[1:0] bits = 1,000 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 REFA Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 23-15 (Rev. 1.1)
Page 355: Temperature Sensor/Reference Voltage Generator (Tsrvr) Characteristics
– – µs TEMP 0x1–0x3 TSRVR_nVCTL.VREFAMD[1:0] Invalid Valid VREFAn VREFA TSRVR_nTCTL.TEMPEN Invalid Valid Temperature sensor output TEMP Temperature sensor output voltage-temperature characteristic = 2.2 to 5.5 V, Typ. value Ta [°C] Seiko Epson Corporation 23-16 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 356 = 100 kW, Ta = 25 °C, Typ. value 1,000 1,000 5.5 V 5.5 V 3.6 V 3.6 V 1.8 V 1.8 V / IC / IC RFCLK RFCLK 1,000 10,000 1,000 10,000 100,000 [k ] [pF] Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 23-17 (Rev. 1.1)
Page 357 = 1,000 pF, Ta = 25 °C, Typ. value 3,000 = 5.5 V = 5.5 V 3.6 V 2,500 1.8 V 2,000 3.6 V 1,500 1,000 1.8 V 1,000 10,000 Ta [°C] [kHz] RFCLK Seiko Epson Corporation 23-18 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 358: Basic External Connection Diagram
*1: For Flash programming *2: When OSC1 crystal oscillator is selected *3: When OSC3 crystal/ceramic oscillator is selected *4: Two-pin output mode *5: Four-pin output mode ( ): Do not mount components if unnecessary. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 24-1 (Rev. 1.1)
Page 359 Symbol Name Recommended components X'tal1 32 kHz crystal resonator C-002RX (R = 50 kW (Max.), C = 7 pF) manufactured by Seiko Epson Corporation OSC1 gate capacitor Trimmer capacitor or ceramic capacitor OSC1 drain capacitor Ceramic capacitor X’tal3 Crystal resonator...
Page 360: Package
25 PACKAGE 25 Package TQFP12-32PIN (P-TQFP032-0707-0.80) INDEX 0.30 /0.45 0.09 /0.2 0° /10° /0.7 Figure 25.1 TQFP12-32PIN Package Dimensions Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 25-1 (Rev. 1.1)
Page 361 25 PACKAGE TQFP12-48PIN (P-TQFP048-0707-0.50) INDEX 0.17 /0.27 0.09 /0.2 0° /10° /0.7 Figure 25.2 TQFP12-48PIN Package Dimensions Seiko Epson Corporation 25-2 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 362 25 PACKAGE QFP13-64PIN (P-LQFP064-1010-0.50) INDEX 0.13 /0.27 0.09 /0.2 0° /10° /0.75 Figure 25.3 QFP13-64PIN Package Dimensions Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 25-3 (Rev. 1.1)
Page 363: Appendix A List Of Peripheral Circuit Control Registers
– – – 0046 (CLG OSC1 Control OSDRB R/WP Register) OSDEN R/WP OSC1BUP R/WP OSC1SELCR R/WP 10–8 CGI1[2:0] R/WP 7–6 INV1B[1:0] R/WP 5–4 INV1N[1:0] R/WP 3–2 – – 1–0 OSC1WT[1:0] R/WP Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL AP-A-1 (Rev. 1.1)
Page 364: Cache Controller (Cache)
0x0020 0080 Cache Controller (CACHE) Address Register name Bit name Initial Reset Remarks 0x0020 CACHECTL 15–8 – 0x00 – – 0080 (CACHE Control 7–2 – 0x00 – Register) – – CACHEEN Seiko Epson Corporation AP-A-2 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 365: 0X0020 00A0-0X0020 00A4 Watchdog Timer (Wdt2)
11–8 RTCHLA[3:0] – – 6–4 RTCMIHA[2:0] 3–0 RTCMILA[3:0] 0x0020 RTCASWCTL 15–12 BCD10[3:0] – 00c6 (RTCA Stopwatch 11–8 BCD100[3:0] Control Register) 7–5 – – SWRST Read as 0. 3–1 – – – SWRUN Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL AP-A-3 (Rev. 1.1)
Page 366 T1MINIF T1SECIF T1_2SECIF T1_4SECIF T1_8SECIF T1_32SECIF 0x0020 RTCAINTE RTCTRMIE – 00d2 (RTCA Interrupt En- SW1IE able Register) SW10IE SW100IE 11–9 – – ALARMIE T1DAYIE T1HURIE T1MINIE T1SECIE T1_2SECIE T1_4SECIE T1_8SECIE T1_32SECIE Seiko Epson Corporation AP-A-4 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 367 Flash Controller (FLASHC) Address Register name Bit name Initial Reset Remarks 0x0020 FLASHCWAIT 15–9 – 0x00 – – 01b0 (FLASHC Flash Read (reserved) R/WP Cycle Register) 7–2 – 0x00 – 1–0 RDWAIT[1:0] R/WP Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL AP-A-5 (Rev. 1.1)
Page 368 – – ✓ P0REN6 – ✓ ✓ P0REN5 – ✓ ✓ P0REN4 – ✓ ✓ P0REN3 – ✓ ✓ P0REN2 – ✓ ✓ P0REN1 – – ✓ P0REN0 – – ✓ Seiko Epson Corporation AP-A-6 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 369 Select Register) 11–10 P05MUX[1:0] – ✓ ✓ 9–8 P04MUX[1:0] – ✓ ✓ 7–6 P03MUX[1:0] – ✓ ✓ 5–4 P02MUX[1:0] – ✓ ✓ 3–2 P01MUX[1:0] – – ✓ 1–0 P00MUX[1:0] – – ✓ Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL AP-A-7 (Rev. 1.1)
Page 370 Flag Register) ing 1. P1IF6 ✓ ✓ ✓ P1IF5 ✓ ✓ ✓ P1IF4 ✓ ✓ ✓ P1IF3 ✓ ✓ ✓ P1IF2 ✓ ✓ ✓ P1IF1 – – ✓ P1IF0 – – ✓ Seiko Epson Corporation AP-A-8 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 371 – – ✓ P2IN6 – – ✓ P2IN5 – – ✓ P2IN4 – – ✓ P2IN3 – ✓ ✓ P2IN2 – ✓ ✓ P2IN1 – ✓ ✓ P2IN0 ✓ ✓ ✓ Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL AP-A-9 (Rev. 1.1)
Page 372 – – ✓ P2IE6 – – ✓ P2IE5 – – ✓ P2IE4 – – ✓ P2IE3 – ✓ ✓ P2IE2 – ✓ ✓ P2IE1 – ✓ ✓ P2IE0 ✓ ✓ ✓ Seiko Epson Corporation AP-A-10 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 373 – – ✓ P3OEN6 – – ✓ P3OEN5 – ✓ ✓ P3OEN4 – ✓ ✓ P3OEN3 – ✓ ✓ P3OEN2 ✓ ✓ ✓ P3OEN1 ✓ ✓ ✓ P3OEN0 – – ✓ Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL AP-A-11 (Rev. 1.1)
Page 374 Filter Enable Register) P3CHATEN6 – – ✓ P3CHATEN5 – ✓ ✓ P3CHATEN4 – ✓ ✓ P3CHATEN3 – ✓ ✓ P3CHATEN2 ✓ ✓ ✓ P3CHATEN1 ✓ ✓ ✓ P3CHATEN0 – – ✓ Seiko Epson Corporation AP-A-12 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 375 7–6 – – – – – – P4OEN5 – – ✓ ✓ P4OEN4 ✓ ✓ ✓ P4OEN3 ✓ ✓ ✓ P4OEN2 ✓ ✓ ✓ P4OEN1 – – ✓ P4OEN0 – – ✓ Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL AP-A-13 (Rev. 1.1)
Page 376 7–6 – – – – – Register) P4SEL5 – – ✓ ✓ P4SEL4 ✓ ✓ ✓ P4SEL3 ✓ ✓ ✓ P4SEL2 ✓ ✓ ✓ P4SEL1 – – ✓ P4SEL0 – – ✓ Seiko Epson Corporation AP-A-14 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 377 – – P5REN6 – – ✓ ✓ P5REN5 – ✓ ✓ P5REN4 ✓ ✓ ✓ P5REN3 – – ✓ P5REN2 – – ✓ P5REN1 ✓ ✓ ✓ P5REN0 ✓ ✓ ✓ Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL AP-A-15 (Rev. 1.1)
Page 378 Select Register) 11–10 P55MUX[1:0] – ✓ ✓ 9–8 P54MUX[1:0] ✓ ✓ ✓ 7–6 P53MUX[1:0] – – ✓ 5–4 P52MUX[1:0] – – ✓ 3–2 P51MUX[1:0] ✓ ✓ ✓ 1–0 P50MUX[1:0] ✓ ✓ ✓ Seiko Epson Corporation AP-A-16 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 379 Flag Register) P6IF5 Cleared by writ- ✓ ✓ ✓ ing 1. P6IF4 ✓ ✓ ✓ P6IF3 ✓ ✓ ✓ P6IF2 ✓ ✓ ✓ P6IF1 ✓ ✓ ✓ P6IF0 ✓ ✓ ✓ Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL AP-A-17 (Rev. 1.1)
Page 380 ✓ ✓ ✓ PDIEN0 ✓ ✓ ✓ 7–4 – – – – – – PDOEN3 – ✓ ✓ ✓ PDOEN2 ✓ ✓ ✓ PDOEN1 ✓ ✓ ✓ PDOEN0 ✓ ✓ ✓ Seiko Epson Corporation AP-A-18 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 381: 0X0020 0300-0X0020 031E Universal Port Multiplexer (Upmux)
4–3 P02PERICH[1:0] 2–0 P02PERISEL[2:0] 0x0020 UPMUXP0MUX2 15–13 P05PPFNC[2:0] – – ✓ ✓ 0304 (P04–05 Universal 12–11 P05PERICH[1:0] Port Multiplexer 10–8 P05PERISEL[2:0] Setting Register) 7–5 P04PPFNC[2:0] – ✓ ✓ 4–3 P04PERICH[1:0] 2–0 P04PERISEL[2:0] Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL AP-A-19 (Rev. 1.1)
Page 382 4–3 P24PERICH[1:0] 2–0 P24PERISEL[2:0] 0x0020 UPMUXP2MUX3 15–13 P27PPFNC[2:0] – – – ✓ 0316 (P26–27 Universal 12–11 P27PERICH[1:0] Port Multiplexer 10–8 P27PERISEL[2:0] Setting Register) 7–5 P26PPFNC[2:0] – – ✓ 4–3 P26PERICH[1:0] 2–0 P26PERISEL[2:0] Seiko Epson Corporation AP-A-20 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 383: Uart (Uart3) Ch.0
0x00 – – 0386 (UART3 Ch.0 Control 7–2 – 0x00 – Register) SFTRST MODEN 0x0020 UART3_0TXD 15–8 – 0x00 – – 0388 (UART3 Ch.0 Trans- 7–0 TXD[7:0] 0x00 mit Data Register) Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL AP-A-21 (Rev. 1.1)
Page 384 0x0020 T16_1CTL 15–9 – 0x00 – – 03a4 (T16 Ch.1 Control PRUN Register) 7–2 – 0x00 – PRESET MODEN 0x0020 T16_1TR 15–0 TR[15:0] 0xffff – 03a6 (T16 Ch.1 Reload Data Register) Seiko Epson Corporation AP-A-22 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 385 – Buffer Empty DMA Request Enable 3–0 TBEDMAEN[3:0] Register) 0x0020 SPIA_0RBFDMAEN 15–8 – 0x00 – – 03be (SPIA Ch.0 Receive 7–4 – – Buffer Full DMA Request Enable 3–0 RBFDMAEN[3:0] Register) Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL AP-A-23 (Rev. 1.1)
Page 386: 0X0020 03C0-0X0020 03D6
I2C_0RXD register. TBEIF H0/S0 Cleared by writing to the I2C_0TXD register. 0x0020 I2C_0INTE 15–8 – 0x00 – – 03d2 (I2C Ch.0 Interrupt BYTEENDIE Enable Register) GCIE NACKIE STOPIE STARTIE ERRIE RBFIE TBEIE Seiko Epson Corporation AP-A-24 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 387: 0X0020 0400-0X0020 042C 16-Bit Pwm Timer (T16B) Ch.0
CAPI2 CAPI1 CAPI0 UP_DOWN 0x0020 T16B_0INTF 15–10 – 0x00 – – 040a (T16B Ch.0 Interrupt CAPOW3IF Cleared by writing 1. Flag Register) CMPCAP3IF CAPOW2IF CMPCAP2IF CAPOW1IF CMPCAP1IF CAPOW0IF CMPCAP0IF CNTMAXIF CNTZEROIF Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL AP-A-25 (Rev. 1.1)
Page 388 – 041a (T16B Ch.0 Compare/ Capture 1 Data Register) 0x0020 T16B_0CC1DMAEN 15–8 – 0x00 – – 041c (T16B Ch.0 Compare/ 7–4 – – Capture 1 DMA Request Enable 3–0 CC1DMAEN[3:0] Register) Seiko Epson Corporation AP-A-26 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 389: 0X0020 0440-0X0020 046C 16-Bit Pwm Timer (T16B) Ch.1
5–4 CNTMD[1:0] ONEST PRESET MODEN 0x0020 T16B_1MC 15–0 MC[15:0] 0xffff – 0444 (T16B Ch.1 Max Counter Data Register) 0x0020 T16B_1TC 15–0 TC[15:0] 0x0000 – 0446 (T16B Ch.1 Timer Counter Data Register) Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL AP-A-27 (Rev. 1.1)
Page 390 – 0452 (T16B Ch.1 Compare/ Capture 0 Data Register) 0x0020 T16B_1CC0DMAEN 15–8 – 0x00 – – 0454 (T16B Ch.1 Compare/ 7–4 – – Capture 0 DMA Request Enable 3–0 CC0DMAEN[3:0] Register) Seiko Epson Corporation AP-A-28 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 391 – 046a (T16B Ch.1 Compare/ Capture 3 Data Register) 0x0020 T16B_1CC3DMAEN 15–8 – 0x00 – – 046c (T16B Ch.1 Compare/ 7–4 – – Capture 3 DMA Request Enable 3–0 CC3DMAEN[3:0] Register) Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL AP-A-29 (Rev. 1.1)
Page 392 (T16 Ch.4 Interrupt 7–1 – 0x00 – Flag Register) UFIF Cleared by writing 1. 0x0020 T16_4INTE 15–8 – 0x00 – – 04ac (T16 Ch.4 Interrupt 7–1 – 0x00 – Enable Register) UFIE Seiko Epson Corporation AP-A-30 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 393: 0X0020 04C0-0X0020 04Cc 16-Bit Timer (T16) Ch.5
(SPIA Ch.2 Interrupt Flag Register) 6–4 – – OEIF H0/S0 Cleared by writing 1. TENDIF H0/S0 RBFIF H0/S0 Cleared by reading the SPIA_2RXD register. TBEIF H0/S0 Cleared by writing to the SPIA_2TXD register. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL AP-A-31 (Rev. 1.1)
Page 394: Uart (Uart3) Ch.1
15–8 – 0x00 – – 0608 (UART3 Ch.1 Trans- 7–0 TXD[7:0] 0x00 mit Data Register) 0x0020 UART3_1RXD 15–8 – 0x00 – – 060a (UART3 Ch.1 Receive 7–0 RXD[7:0] 0x00 Data Register) Seiko Epson Corporation AP-A-32 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 395: Uart (Uart3) Ch.2
3–2 – – 1–0 CLKSRC[1:0] 0x0020 UART3_2MOD 15–13 – 0x00 – – 0622 (UART3 Ch.2 Mode PECAR Register) CAREN BRDIV INVRX INVTX – – PUEN OUTMD IRMD CHLN PREN PRMD STPB Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL AP-A-33 (Rev. 1.1)
Page 396 0660 (T16 Ch.6 Clock DBRUN Control Register) 7–4 CLKDIV[3:0] 3–2 – – 1–0 CLKSRC[1:0] 0x0020 T16_6MOD 15–8 – 0x00 – – 0662 (T16 Ch.6 Mode 7–1 – 0x00 – Register) TRMD Seiko Epson Corporation AP-A-34 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 397: 0X0020 0670-0X0020 067E Synchronous Serial Interface (Spia) Ch.1
7–4 – – Enable Register) OEIE TENDIE RBFIE TBEIE 0x0020 SPIA_1TBEDMAEN 15–8 – 0x00 – – 067c (SPIA Ch.1 Transmit 7–4 – – Buffer Empty DMA Request Enable 3–0 TBEDMAEN[3:0] Register) Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL AP-A-35 (Rev. 1.1)
Page 398 7–4 – – Register) MSTSSO SFTRST MODEN 0x0020 QSPI_0TXD 15–0 TXD[15:0] 0x0000 – 0694 (QSPI Ch.0 Transmit Data Register) 0x0020 QSPI_0RXD 15–0 RXD[15:0] 0x0000 – 0696 (QSPI Ch.0 Receive Data Register) Seiko Epson Corporation AP-A-36 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 399: 0X0020 06C0-0X0020 06D6 I 2 C (I2C) Ch.1
Register name Bit name Initial Reset Remarks 0x0020 I2C_1CLK 15–9 – 0x00 – – 06c0 (I2C Ch.1 Clock DBRUN Control Register) 7–6 – – 5–4 CLKDIV[1:0] 3–2 – – 1–0 CLKSRC[1:0] Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL AP-A-37 (Rev. 1.1)
Page 400 – Buffer Empty DMA Request Enable 3–0 TBEDMAEN[3:0] Register) 0x0020 I2C_1RBFDMAEN 15–8 – 0x00 – – 06d6 (I2C Ch.1 Receive 7–4 – – Buffer Full DMA Request Enable 3–0 RBFDMAEN[3:0] Register) Seiko Epson Corporation AP-A-38 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 401: 0X0020 06E0-0X0020 06F6 I 2 C (I2C) Ch.2
I2C_2RXD register. TBEIF H0/S0 Cleared by writing to the I2C_2TXD register. 0x0020 I2C_2INTE 15–8 – 0x00 – – 06f2 (I2C Ch.2 Interrupt BYTEENDIE Enable Register) GCIE NACKIE STOPIE STARTIE ERRIE RBFIE TBEIE Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL AP-A-39 (Rev. 1.1)
Page 402 15–8 CRDTY[7:0] 0x00 – 0730 (REMC3 Carrier 7–0 CRPER[7:0] 0x00 Waveform Register) 0x0020 REMC3CCTL 15–9 – 0x00 – – 0732 (REMC3 Carrier OUTINVEN Modulation Control 7–1 – 0x00 – Register) CARREN Seiko Epson Corporation AP-A-40 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 403: 0X0020 0780-0X0020 078C 16-Bit Timer (T16) Ch.7
– figuration Register) 1–0 VRANGE[1:0] 0x0020 ADC12A_0INTF 15–9 – 0x00 – – 07a8 (ADC12A Ch.0 OVIF Cleared by writing 1. Interrupt Flag AD7CIF Register) AD6CIF AD5CIF AD4CIF AD3CIF AD2CIF AD1CIF AD0CIF Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL AP-A-41 (Rev. 1.1)
Page 404: 0X0020 07C0-0X0020 07C2 Temperature Sensor
07c0 (TSRVR Ch.0 7–1 – 0x00 Temperature Sensor TEMPEN Control Register) 0x0020 TSRVR_0VCTL 15–8 – 0x00 – – 07c2 (TSRVR Ch.0 7–2 – 0x00 Reference Voltage Generator Control 1–0 VREFAMD[1:0] Register) Seiko Epson Corporation AP-A-42 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 405: 0X0020 0840-0X0020 0850 R/F Converter (Rfc) Ch.0
Register name Bit name Initial Reset Remarks 0x0020 SDAC2CLK 15–9 – 0x00 – – 0860 (SDAC2 Clock Con- DBRUN trol Register) 7–6 – – 5–4 CLKDIV[1:0] 3–2 – – 1–0 CLKSRC[1:0] Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL AP-A-43 (Rev. 1.1)
Page 406 0x00 – – 08a6 (HWP Interrupt 7–1 – 0x00 – Enable Register) HWPIE 0x0020 HWPCMDTRG 15–8 – 0x00 – – 08a8 (HWP Command Trig- 7–1 – 0x00 – ger Register) HWP0TRG Seiko Epson Corporation AP-A-44 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 407: 0X0020 1000-0X0020 2014 Dma Controller (Dmac)
3–0 PASET[3:0] 0x0020 DMACPACLR 31–24 – – – – 1034 (DMAC Primary-Alter- 23–16 – – – nate Clear Register) 15–8 – – – 7–4 – – – 3–0 PACLR[3:0] – – Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL AP-A-45 (Rev. 1.1)
Page 408 – ERRIESET 0x0020 DMACERRIECLR 31–24 – 0x00 – – 2014 (DMAC Error Interrupt 23–16 – 0x00 – Enable Clear Register) 15–8 – 0x00 – 7–1 – 0x00 – ERRIECLR – – Seiko Epson Corporation AP-A-46 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Page 409: Appendix B Power Saving
• Using a crystal resonator with lower C value decreases current consumption. However, these configurations may reduce the oscillation margin and increase the frequency error, therefore, be sure to perform matching evaluation using the actual printed circuit board. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL AP-B-1 (Rev. 1.1)
Page 410: Other Power Saving Methods
Continuous operation mode (SVD3CTL.SVDMD[1:0] bits = 0x0) always detects the power supply voltage, therefore, it increases current consumption. Set the supply voltage detector to intermittent operation mode or turn it on only when required. Seiko Epson Corporation AP-B-2 S1C31D41 TECHNICAL MANUAL...
Page 411: Appendix C Mounting Precautions
Sudden power supply fluctuations due to noise will cause malfunctions. Consider the following issues. (1) Connections from the power supply to the V and V pins should be implemented via the shortest, thick- est patterns possible. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL AP-C-1 (Rev. 1.1)
Page 412 (2) Electromagnetically-induced noise from a solder iron when soldering In particular, during soldering, take care to ensure that the soldering iron GND (tip potential) has the same po- tential as the IC GND. Seiko Epson Corporation AP-C-2 S1C31D41 TECHNICAL MANUAL...
Page 413: Appendix D Measures Against Noise
The resistance value should be determined by evaluating it on the mounting board. When connecting a power supply directly to the VREFA pin, insert a 100 W resistor in series. This resistance does not affect the A/D converter characteristics. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL AP-D-1 (Rev. 1.1)
Page 414: Revision History
REVISION HISTORY Revision History Code No. Page Contents 414190500 New establishment 414190501 1.1 Features Added the following annotation to Table 1.1.1. *2 SLEEP mode refers to deep sleep mode in the Cortex ® -M0+ processor. The RAM retains data even in SLEEP mode.
Page 415 REVISION HISTORY Code No. Page Contents 414190501 16-7 16.4.3 Data Reception in Master Mode Data receiving procedure Added Step 1. (The old step numbers were carried down in order.) 1. When receiving one-byte data, write 1 to the I2CnCTL.TXNACK bit. 16-9 16.4.3 Data Reception in Master Mode Data reception using DMA...
Page 416 Fax: +86-10-3299-0560 Epson Europe Electronics GmbH Riesstrasse 15, 80992 Munich, Germany Phone: +49-89-14005-0 Fax: +49-89-14005-110 Epson Taiwan Technology & Trading Ltd. 15F, No.100, Songren Rd, Sinyi Dist, Taipei City 110, Taiwan Phone: +886-2-8786-6688 Epson Singapore Pte., Ltd. 1 HarbourFront Place,...

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