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Clock generator (CLG)
System clock source
System clock frequency (operating
frequency)
IOSC oscillator circuit (boot clock
source)
OSC1 oscillator circuit
OSC3 oscillator circuit
EXOSC clock input
Other
I/O port (PPORT)
Number of general-purpose I/O ports
Number of input interrupt ports
Number of ports that support
universal port multiplexer (UPMUX)
Timers
Watchdog timer (WDT2)
Real-time clock (RTCA)
16-bit timer (T16)
16-bit PWM timer (T16B)
Supply voltage detector (SVD3)
Number of channels
Detection voltage
Detection level
Other
12-bit A/D converter (ADC12A)
Conversion method
Resolution
Number of conversion channels
Number of analog signal inputs
R/F converter（RFC）
Conversion method
Number of conversion channels
Supported sensors
IR remote controller (REMC3)
Number of transmitter channels
Other
Reset
#RESET pin
Power-on reset
Brown-out reset
Watchdog timer reset
Supply voltage detector reset
Interrupt
Non-maskable interrupt
Programmable interrupt
1-2
4 sources (IOSC/OSC1/OSC3/EXOSC)
V
voltage mode = mode0: 16 MHz (max.)
D1
V
voltage mode = mode1: 1.8 MHz (max.)
D1
V
voltage mode = mode0: 8/2/1 MHz (typ.) software selectable
D1
V
voltage mode = mode1: 1.8/0.9 MHz (typ.) software selectable
D1
10 µs (typ.) starting time (time from cancelation of SLEEP state to vector table read
by the CPU)
32.768 kHz (typ.) crystal oscillator
32kHz (typ.) embedded oscillator
Oscillation stop detection circuit included
16 MHz (max.) crystal/ceramic oscillator
16/8/4MHz(typ) embedded oscillator
16 MHz (max.) square or sine wave input
Configurable system clock division ratio
Configurable system clock used at wake up from SLEEP state
Operating clock frequency for the CPU and all peripheral circuits is selectable.
PKG48pin : 39bits(max.)
PKG64pin : 55bits(max.)
PKG80pin : 71bits(max.)
PKG100pin : 91bits(max.)
Pins are shared with the peripheral I/O.
PKG48pin : 33bits(max.)
PKG64pin : 49bits(max.)
PKG80pin : 65bits(max.)
PKG100pin : 85bits(max.)
PKG48pin : 16bits(max.)
PKG64pin : 24bits(max.)
PKG80pin : 27bits(max.)
PKG100pin : 32bits(max.)
A peripheral circuit I/O function selected via software can be assigned to each port.
Generates NMI or watchdog timer reset.
Programmable NMI/reset generation cycle
128–1 Hz counter, second/minute/hour/day/day of the week/month/year counters
Theoretical regulation function for 1-second correction
Alarm and stopwatch functions
8 channels
Generates the SPIA and QSPI master clocks, and the ADC12A operating clock/
trigger signal.
2 channels
Event counter/capture function
PWM waveform generation function
Number of PWM output or capture input ports: 4 ports/channel
1 channel
V
or an external voltage (2 external detection ports are available.)
DD
V
: 28 levels (1.8 to 5.0 V)/external voltage: 32 levels (1.2 to 5.0 V)
DD
Intermittent operation mode
Generates an interrupt or reset according to the detection level evaluation.
Successive approximation type
12 bits
1 channel
8 ports/channel (max)
CR oscillation type 24-bit counters
1 channel
DC bias resistive sensors
1 channel
EL lamp drive waveform can be generated (by the hardware) for an application
Output inversion function
ex- ample.
Reset when the reset pin is set to low.
Reset at power on.
Reset when the power supply voltage drops (when V
Reset when the watchdog timer overflows (can be enabled/disabled using a
register).
Reset when the supply voltage detector detects the set voltage level (can be
enabled/ disabled using a register).
6 systems (Reset, NMI, HardFault, SVCall, PendSV, SysTic)
External interrupt: 3 systems
Internal interrupt: 27 systems
Seiko Epson Corporation
≤ 1.45 V (typ.) is detected).
DD
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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