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ADC12A Ch.n Interrupt Enable Register
Register name
Bit
ADC12A_nINTE
15–9
8
7
6
5
4
3
2
1
0
Bits 15–9
Reserved
Bit 8
OVIE
Bits 7–0
ADmIE
These bits enable ADC12A interrupts.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
The following shows the correspondence between the bit and interrupt:
ADC12A_nINTE.OVIE bit:
ADC12A_nINTE.ADmCIE bit: Analog input signal m A/D conversion completion interrupt
ADC12A Ch.n DMA Request Enable Register m
Register name
Bit
ADC12A_nDMAENm 15–0
Bits 15–0
ADCDMAEN[15:0]
These bits enable ADC12A to issue a DMA transfer request to the corresponding DMA
controller channel (Ch.0–Ch.15) when the A/D conversion for each analog input has
completed.
1 (R/W): Enable DMA transfer request
0 (R/W): Disable DMA transfer request
Each bit corresponds to a DMA controller channel. The high-order bits for the
unimplemented channels are ineffective.
ADC12A Ch.n Result Register
Register name
Bit
ADC12A_nADD
15–0
Bits 15–0
ADD[15:0]
The A/D conversion results are set to these bits.
19-12
Bit name
Initial
–
0x00
OVIE
0
AD7IE
0
AD6IE
0
AD5IE
0
AD4IE
0
AD3IE
0
AD2IE
0
AD1IE
0
AD0IE
0
A/D conversion result overwrite error interrupt
Bit name
Initial
ADCDMAEN[15:0]
0x0000
Bit name
Initial
ADD[15:0]
0x0000
Seiko Epson Corporation
Reset
R/W
–
R
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
Reset
R/W
H0
R/W
Reset
R/W
H0
R
Remarks
–
Remarks
–
Remarks
–
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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