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16.6. DMA Transfer Requests
The I2C has a function to generate DMA transfer requests from the causes shown in Table 16.6.1.
Cause to
DMA transfer
request
request flag
DMA transfer
Receive
buffer
Receive buffer full flag
full
(I2C_nINTF.RBFIF)
Transmit
buffer
Transmit buffer empty
empty
flag (I2C_nINTF.TBEIF)
The I2C provides DMA transfer request enable bits corresponding to each DMA transfer request flag
shown above for the number of DMA channels. A DMA transfer request is sent to the pertinent channel
of the DMA controller only when the DMA transfer request flag, of which DMA transfer has been enabled
by the DMA transfer request enable bit, is set. The DMA transfer request flag also serves as an interrupt
flag, therefore, both the DMA transfer request and the interrupt cannot be enabled at the same time.
After a DMA transfer has completed, disable the DMA transfer to prevent unintended DMA transfer
requests from being issued. For more information on the DMA control, refer to the "DMA Controller"
chapter.
16-20
Table 16.6.1 DMA Transfer Request Causes of I2C
Set condition
When received data is loaded to the re-
ceive data buffer
Master mode: When a START condition is
issued or when an ACK is received from the
slave
Slave mode: When transmit data written to
the transmit data buffer is transferred to
theshift register or when an address match
is detected with R/W bit set to 1
Seiko Epson Corporation
Clear condition
Reading
received
data
empty the receive data buffer),
software reset
Writing transmit data
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
(to
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