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Data transmission
Set the transfer direction to output
(QSPI_nCTL.DIR = 0)
Assert the slave select signal output from
the #QSPISSn pin (QSPI_nCTL.MSTSSO
= 0) or a general-purpose port
Read the QSPI_nINTF.TBEIF bit
QSPI_nINTF.TBEIF = 1 ?
Write transmit data to
the QSPI_nTXD register
Transmit data remained?
Negate the slave select signal output from
the #QSPISSn pin (QSPI_nCTL.MSTSSO
= 1) or a general-purpose port
Figure 15.5.4.2 Data Transmission Flowchart in Master Mode
Data transmission using DMA
By setting the QSPI_nTBEDMAEN.TBEDMAENx bit to 1 (DMA transfer request enabled), a DMA
transfer request is sent to the DMA controller and transmit data is transferred from the specified
memory to the QSPI_ nTXD register via DMA Ch.x when the QSPI_nINTF.TBEIF bit is set to 1 (transmit
buffer empty).
This automates the procedure from Step 3 to Step 6 described above.
The transfer source/destination and control data must be set for the DMA controller and the
relevant DMA channel must be enabled to start a DMA transfer in advance so that transmit data
will be transferred to the QSPI_nTXD register. For more information on DMA, refer to the "DMA
Controller" chapter.
Table 15.5.4.1 DMA Data Structure Configuration Example (for 16-bit Data Transmission)
Item
End pointer
Transfer source
Transfer destination QSPI_nTXD register address
Control data dst_inc
dst_size
src_inc
src_size
R_power
n_minus_1
cycle_ctrl
15-14
No
Yes
Yes
No
Wait for an interrupt request
(QSPI_nINTF.TBEIF = 1)
End
Memory address in which the last transmit data is stored
0x3 (no increment)
0x1 (haflword)
0x1 (+2)
0x1 (halfword)
0x0 (arbitrated for every transfer)
Number of transfer data
0x1 (basic transfer)
Seiko Epson Corporation
Setting example
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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