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(4) Continuous conversion mode (ADC12A_nTRG.CNVMD bit = 1)
A/D conversion for ADINn3–4 (ADC12A_nTRG.STAAIN[2:0] bits = 0x3, ADC12A_nTRG.ENDAIN[2:0] bits =
0x4) Software trigger (ADC12A_nTRG.CNVTRG[1:0] bits = 0x0)
ADC12A_nCTL.ADST
ADC12A_nCTL.BSYSTAT
ADC12A_nCTL.ADSTAT[2:0]
ADINn3 ADINn3
A/D conversion operations
ADC12A_nADD.ADD[15:0]
ADC12A_nINTF.AD3CIF
ADC12A_nINTF.AD4CIF
A/D converted data transfer using DMA
By setting the ADC12A_nDMAEN.ADCDMAENx bit to 1 (DMA transfer request enabled), a DMA
transfer request is sent to the DMA controller and the ADC12A_nADD register value is transferred to
the specified memory via DMA Ch.x when the ADC12A_nINTF.ADmCIF bit is set to 1 (when A/D
conversion for the analog input signal m has completed).
This automates reading and saving of A/D converted data.
The transfer source/destination and control data must be set for the DMA controller and the
relevant DMA channel must be enabled to start a DMA transfer in advance. For more information
on DMA, refer to the "DMA Controller" chapter.
Table 19.4.4.1 DMA Data Structure Configuration Example (Capture Data Transfer)
Item
End pointer
Transfer source
Transfer destination Memory address to which the last A/D converted data is stored
Control data dst_inc
dst_size
src_inc
src_size
R_power
n_minus_1
cycle_ctrl
19-6
A/D converting
0x3 (ADINn3)
0x4 (ADINn4)
Sampling
Sampling
Conversion
Conversion
ADINn3 ADINn3 ADINn3 ADINn3
First ADINn3
result
Cleared
Figure 19.4.4.1 A/D Conversion Operations
ADC12A_nADD register address
0x1 (+2)
0x1 (haflword)
0x3 (no increment)
0x1 (halfword)
0x0 (arbitrated for every transfer)
Number of transfer data
0x1 (basic transfer)
Seiko Epson Corporation
0x3 (ADINn3)
0x4 (ADINn4)
Sampling
Sampling
Conversion
Conversion
ADINn3 ADINn3
First ADINn4
Second ADINn3
result
result
Cleared
Cleared
Setting example
0x5 (ADINn5)
Second ADINn4
result
Cleared
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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