User Manuals: Epson S1C31W74 32-Bit Microcontroller

Manuals and User Guides for Epson S1C31W74 32-Bit Microcontroller. We have 1 Epson S1C31W74 32-Bit Microcontroller manual available for free PDF download: Technical Manual

Epson S1C31W74 Technical Manual (434 pages)

CMOS 32-BIT SINGLE CHIP MICROCONTROLLER

Brand: Epson | Category: Microcontrollers | Size: 11 MB

Table of Contents
4
Overview
16
Features
16
Block Diagram
18
Pins
19
Pin Configuration Diagram
19
Pad Configuration Diagram
20
Pin Descriptions
22
Power Supply, Reset, and Clocks
26
Power Generator (PWGA)
26
Overview
26
Pins
26
D1 Regulator Operation Mode
27
D1 Regulator Voltage Mode
27
System Reset Controller (SRC)
28
Overview
28
Input Pin
28
Reset Sources
29
Initialization Conditions (Reset Groups)
29
Clock Generator (CLG)
30
Overview
30
Input/Output Pins
31
Clock Sources
32
Operations
33
Operating Mode
38
Initial Boot Sequence
38
Transition between Operating Modes
38
Interrupts
40
Control Registers
40
PWGA Control Register
40
CLG System Clock Control Register
41
CLG Oscillation Control Register
42
CLG IOSC Control Register
43
CLG OSC1 Control Register
43
CLG OSC3 Control Register
45
CLG Interrupt Flag Register
45
CLG Interrupt Enable Register
46
CLG FOUT Control Register
47
CPU and Debugger
48
Overview
48
Cpu
48
Debugger
48
List of Debugger Input/Output Pins
48
External Connection
48
Reference Documents
49
Memory and Bus
50
Overview
50
Bus Access Cycle
51
Flash Memory
51
Flash Memory Pin
51
Flash Bus Access Cycle Setting
51
Flash Programming
52
Ram
52
Display Data RAM
52
Peripheral Circuit Control Registers
52
System-Protect Function
58
Instruction Cache
58
Memory Mapped Access Area for External Flash Memory
58
Control Registers
59
System Protect Register
59
CACHE Control Register
59
FLASHC Flash Read Cycle Register
59
Interrupt
60
Overview
60
Vector Table
60
Vector Table Offset Address (VTOR)
62
Priority of Interrupts
62
Peripheral Circuit Interrupt Control
62
Nmi
63
DMA Controller (DMAC)
64
Overview
64
Operations
65
Initialization
65
Priority
65
Data Structure
65
Transfer Source End Pointer
66
Transfer Destination End Pointer
66
Control Data
66
DMA Transfer Mode
68
Basic Transfer
68
Auto-Request Transfer
68
Ping-Pong Transfer
69
Memory Scatter-Gather Transfer
70
Peripheral Scatter-Gather Transfer
71
DMA Transfer Cycle
72
Interrupts
72
Control Registers
73
DMAC Status Register
73
DMAC Configuration Register
73
DMAC Control Data Base Pointer Register
74
DMAC Alternate Control Data Base Pointer Register
74
DMAC Software Request Register
74
DMAC Request Mask Set Register
74
DMAC Request Mask Clear Register
75
DMAC Enable Set Register
75
DMAC Enable Clear Register
75
DMAC Primary-Alternate Set Register
75
DMAC Primary-Alternate Clear Register
76
DMAC Priority Set Register
76
DMAC Priority Clear Register
76
DMAC Error Interrupt Flag Register
76
DMAC Transfer Completion Interrupt Flag Register
77
DMAC Transfer Completion Interrupt Enable Set Register
77
DMAC Transfer Completion Interrupt Enable Clear Register
77
DMAC Error Interrupt Enable Set Register
77
DMAC Error Interrupt Enable Clear Register
78
O Ports (PPORT)
79
Overview
79
I/O Cell Structure and Functions
80
Schmitt Input
80
Over Voltage Tolerant Fail-Safe Type I/O Cell
80
Pull-Up/Pull-Down
80
CMOS Output and High Impedance State
81
Clock Settings
81
PPORT Operating Clock
81
Clock Supply in SLEEP Mode
81
Clock Supply During Debugging
81
Operations
81
Initialization
81
Port Input/Output Control
83
Interrupts
84
Control Registers
84
Px Port Data Register
84
Px Port Enable Register
85
Px Port Pull-Up/Down Control Register
85
Px Port Interrupt Flag Register
86
Px Port Interrupt Control Register
86
Px Port Chattering Filter Enable Register
86
Px Port Mode Select Register
86
Px Port Function Select Register
87
P Port Clock Control Register
87
P Port Interrupt Flag Group Register
88
Control Register and Port Function Configuration of this IC
89
P0 Port Group
89
P1 Port Group
90
P2 Port Group
91
P3 Port Group
92
P4 Port Group
93
P5 Port Group
94
P6 Port Group
95
P7 Port Group
96
P8 Port Group
97
P9 Port Group
98
Pd Port Group
99
Common Registers between Port Groups
100
Universal Port Multiplexer (UPMUX)
101
Overview
101
Peripheral Circuit I/O Function Assignment
101
Control Registers
102
Pxy-Xz Universal Port Multiplexer Setting Register
102
Watchdog Timer (WDT2)
103
Overview
103
Clock Settings
103
WDT2 Operating Clock
103
Clock Supply in DEBUG Mode
103
Operations
104
WDT2 Control
104
Operations in HALT and SLEEP Modes
105
Control Registers
105
WDT2 Clock Control Register
105
WDT2 Control Register
106
WDT2 Counter Compare Match Register
107
Real-Time Clock (RTCA)
108
Overview
108
Output Pin and External Connection
108
Output Pin
108
Clock Settings
109
RTCA Operating Clock
109
Theoretical Regulation Function
109
Operations
110
RTCA Control
110
Real-Time Clock Counter Operations
111
Stopwatch Control
111
Stopwatch Count-Up Pattern
111
Interrupts
112
Control Registers
113
RTCA Control Register (Low Byte)
113
RTCA Control Register (High Byte)
114
RTCA Second Alarm Register
114
RTCA Hour/Minute Alarm Register
115
RTCA Stopwatch Control Register
115
RTCA Second/1Hz Register
116
RTCA Hour/Minute Register
117
RTCA Month/Day Register
118
RTCA Year/Week Register
118
RTCA Interrupt Flag Register
119
RTCA Interrupt Enable Register
120
Supply Voltage Detector (SVD2)
122
Overview
122
Input Pin and External Connection
123
Input Pin
123
External Connection
123
Clock Settings
123
SVD2 Operating Clock
123
Clock Supply in SLEEP Mode
123
Clock Supply During Debugging
124
Operations
124
SVD2 Control
124
SVD2 Operations
125
SVD2 Interrupt and Reset
126
SVD2 Interrupt
126
SVD2 Reset
126
Control Registers
127
SVD2 Ch.n Clock Control Register
127
S1C31W74 Technical Manual
127
Seiko Epson Corporation
127
SVD2 Ch.n Control Register
127
SVD2 Ch.n Status and Interrupt Flag Register
129
SVD2 Ch.n Interrupt Enable Register
129
16-Bit Timers (T16)
130
Overview
130
Input Pin
130
Clock Settings
131
T16 Operating Clock
131
Clock Supply in SLEEP Mode
131
Clock Supply During Debugging
131
Event Counter Clock
131
Operations
131
Initialization
131
Counter Underflow
132
Operations in Repeat Mode
132
Operations in One-Shot Mode
132
Counter Value Read
133
Interrupt
133
Control Registers
133
T16 Ch.n Clock Control Register
133
T16 Ch.n Control Register
134
T16 Ch.n Reload Data Register
135
T16 Ch.n Counter Data Register
135
T16 Ch.n Interrupt Flag Register
135
T16 Ch.n Interrupt Enable Register
136
Uart (Uart2)
137
Overview
137
Input/Output Pins and External Connections
138
List of Input/Output Pins
138
External Connections
138
Input Pin Pull-Up Function
138
Output Pin Open-Drain Output Function
138
Input/Output Signal Inverting Function
138
Clock Settings
138
UART2 Operating Clock
138
Clock Supply in SLEEP Mode
139
Clock Supply During Debugging
139
Baud Rate Generator
139
Data Format
139
Operations
140
Initialization
140
Data Transmission
141
Data Reception
142
Irda Interface
143
Receive Errors
144
Framing Error
144
Parity Error
145
Overrun Error
145
Interrupts
145
DMA Transfer Requests
145
Control Registers
146
UART2 Ch.n Clock Control Register
146
UART2 Ch.n Mode Register
147
UART2 Ch.n Baud-Rate Register
148
UART2 Ch.n Control Register
148
UART2 Ch.n Transmit Data Register
149
UART2 Ch.n Receive Data Register
149
UART2 Ch.n Status and Interrupt Flag Register
149
UART2 Ch.n Interrupt Enable Register
150
UART2 Ch.n Transmit Buffer Empty DMA Request Enable Register
151
UART2 Ch.n Receive Buffer One Byte Full DMA Request Enable Register
151
Synchronous Serial Interface (SPIA)
152
Overview
152
Input/Output Pins and External Connections
153
List of Input/Output Pins
153
External Connections
153
Pin Functions in Master Mode and Slave Mode
154
Input Pin Pull-Up/Pull-Down Function
154
Clock Settings
154
SPIA Operating Clock
154
Clock Supply During Debugging
155
SPI Clock (Spiclkn) Phase and Polarity
155
Data Format
156
Operations
156
Initialization
156
Data Transmission in Master Mode
157
Data Reception in Master Mode
159
Terminating Data Transfer in Master Mode
161
Data Transfer in Slave Mode
161
Terminating Data Transfer in Slave Mode
162
Interrupts
163
DMA Transfer Requests
164
Control Registers
164
SPIA Ch.n Mode Register
164
SPIA Ch.n Control Register
165
SPIA Ch.n Transmit Data Register
166
SPIA Ch.n Receive Data Register
166
SPIA Ch.n Interrupt Flag Register
166
SPIA Ch.n Interrupt Enable Register
167
SPIA Ch.n Transmit Buffer Empty DMA Request Enable Register
167
SPIA Ch.n Receive Buffer Full DMA Request Enable Register
167
Quad Synchronous Serial Interface (QSPI)
168
Overview
168
Input/Output Pins and External Connections
169
List of Input/Output Pins
169
External Connections
169
Pin Functions in Master Mode and Slave Mode
173
Input Pin Pull-Up/Pull-Down Function
173
Clock Settings
173
QSPI Operating Clock
173
Clock Supply During Debugging
174
QSPI Clock (Qspiclkn) Phase and Polarity
174
Data Format
175
Operations
176
Register Access Mode
176
Memory Mapped Access Mode
177
Initialization
178
Data Transmission in Master Mode
179
Data Reception in Register Access Master Mode
181
Data Reception in Memory Mapped Access Mode
184
Terminating Memory Mapped Access Operations
192
Terminating Data Transfer in Master Mode
192
Data Transfer in Slave Mode
193
Terminating Data Transfer in Slave Mode
194
Interrupts
194
DMA Transfer Requests
195
Control Registers
196
QSPI Ch.n Mode Register
196
QSPI Ch.n Control Register
198
QSPI Ch.n Transmit Data Register
199
QSPI Ch.n Receive Data Register
199
QSPI Ch.n Interrupt Flag Register
199
QSPI Ch.n Interrupt Enable Register
200
QSPI Ch.n Transmit Buffer Empty DMA Request Enable Register
200
QSPI Ch.n Receive Buffer Full DMA Request Enable Register
201
QSPI Ch.n FIFO Data Ready DMA Request Enable Register
201
QSPI Ch.n Remapping Start Address High Register
202
QSPI Ch.n Memory Mapped Access Configuration Register 2
202
QSPI Ch.n Mode Byte Register
204
C (I2C)
205
Overview
205
Input/Output Pins and External Connections
206
List of Input/Output Pins
206
External Connections
206
Clock Settings
207
I2C Operating Clock
207
Clock Supply During Debugging
207
Baud Rate Generator
207
Operations
208
Initialization
208
Data Transmission in Master Mode
209
Data Reception in Master Mode
211
10-Bit Addressing in Master Mode
214
Data Transmission in Slave Mode
215
Data Reception in Slave Mode
217
Slave Operations in 10-Bit Address Mode
219
Automatic Bus Clearing Operation
219
Error Detection
220
Interrupts
221
DMA Transfer Requests
222
Control Registers
222
I2C Ch.n Clock Control Register
222
I2C Ch.n Mode Register
223
I2C Ch.n Baud-Rate Register
223
I2C Ch.n Own Address Register
224
I2C Ch.n Control Register
224
I2C Ch.n Transmit Data Register
225
I2C Ch.n Receive Data Register
225
I2C Ch.n Status and Interrupt Flag Register
226
I2C Ch.n Interrupt Enable Register
227
I2C Ch.n Transmit Buffer Empty DMA Request Enable Register
228
I2C Ch.n Receive Buffer Full DMA Request Enable Register
228
16-Bit PWM Timers (T16B)
229
Overview
229
Input/Output Pins
230
Clock Settings
231
T16B Operating Clock
231
Clock Supply in SLEEP Mode
231
Clock Supply During Debugging
231
Event Counter Clock
231
Operations
232
Initialization
232
Counter Block Operations
233
Comparator/Capture Block Operations
236
TOUT Output Control
245
Interrupt
251
DMA Transfer Requests
251
Control Registers
251
T16B Ch.n Clock Control Register
251
T16B Ch.n Counter Control Register
252
T16B Ch.n Max Counter Data Register
253
T16B Ch.n Timer Counter Data Register
253
T16B Ch.n Counter Status Register
254
T16B Ch.n Interrupt Flag Register
255
T16B Ch.n Interrupt Enable Register
256
T16B Ch.n Comparator/Capture M Control Register
257
T16B Ch.n Compare/Capture M Data Register
259
T16B Ch.n Counter Max/Zero DMA Request Enable Register
260
T16B Ch.n Compare/Capture M DMA Request Enable Register
260
Sound Generator (SNDA)
261
Overview
261
Output Pins and External Connections
262
List of Output Pins
262
Output Pin Drive Mode
262
External Connections
262
Clock Settings
263
SNDA Operating Clock
263
Clock Supply in SLEEP Mode
263
Clock Supply in DEBUG Mode
263
Operations
263
Initialization
263
Buzzer Output in Normal Buzzer Mode
263
Buzzer Output in One-Shot Buzzer Mode
266
Output in Melody Mode
267
Interrupts
269
DMA Transfer Requests
270
Control Registers
270
SNDA Clock Control Register
270
SNDA Select Register
271
SNDA Control Register
272
SNDA Data Register
272
SNDA Interrupt Flag Register
273
SNDA Interrupt Enable Register
273
SNDA Sound Buffer Empty DMA Request Enable Register
274
IR Remote Controller (REMC2)
275
Overview
275
Input/Output Pins and External Connections
275
Output Pin
275
External Connections
276
Clock Settings
276
REMC2 Operating Clock
276
Clock Supply in SLEEP Mode
276
Clock Supply During Debugging
276
Operations
276
Initialization
276
Data Transmission Procedures
277
REMO Output Waveform
277
Continuous Data Transmission and Compare Buffers
279
Interrupts
280
Application Example: Driving el Lamp
281
Control Registers
281
REMC2 Clock Control Register
281
REMC2 Data Bit Counter Control Register
282
REMC2 Data Bit Counter Register
283
REMC2 Data Bit Active Pulse Length Register
284
REMC2 Data Bit Length Register
284
REMC2 Status and Interrupt Flag Register
284
REMC2 Interrupt Enable Register
285
REMC2 Carrier Waveform Register
285
REMC2 Carrier Modulation Control Register
285
LCD Driver (LCD32B)
287
Overview
287
Output Pins and External Connections
288
List of Output Pins
288
External Connections
288
Clock Settings
289
LCD32B Operating Clock
289
Clock Supply in SLEEP Mode
289
Clock Supply During Debugging
289
Frame Frequency
289
LCD Power Supply
292
Internal Generation Mode
292
External Voltage Application Mode
292
LCD Voltage Regulator Settings
293
LCD Voltage Booster Setting
293
LCD Contrast Adjustment
293
Operations
293
Initialization
293
Display On/Off
294
Inverted Display
294
Drive Duty Switching
294
Drive Waveforms
296
Partial Common Output Drive
302
N-Segment-Line Inverse AC Drive
302
Display Data RAM
303
Display Area Selection
303
Segment Pin Assignment
303
Common Pin Assignment
303
Interrupt
312
Control Registers
312
LCD32B Clock Control Register
312
LCD32B Control Register
313
LCD32B Timing Control Register 1
313
LCD32B Timing Control Register 2
314
LCD32B Power Control Register
314
LCD32B Display Control Register
315
LCD32B COM Pin Control Registers 0 and 1
316
LCD32B Interrupt Flag Register
317
LCD32B Interrupt Enable Register
317
F Converter (RFC)
318
Overview
318
Input/Output Pins and External Connections
319
List of Input/Output Pins
319
Clock Settings
320
RFC Operating Clock
320
Clock Supply in SLEEP Mode
320
Clock Supply in DEBUG Mode
320
Operations
320
Initialization
320
Operating Modes
321
RFC Counters
321
Converting Operations and Control Procedure
322
CR Oscillation Frequency Monitoring Function
324
Interrupts
324
Control Registers
325
RFC Ch.n Clock Control Register
325
RFC Ch.n Control Register
325
RFC Ch.n Oscillation Trigger Register
326
RFC Ch.n Measurement Counter Low and High Registers
327
RFC Ch.n Time Base Counter Low and High Registers
327
RFC Ch.n Interrupt Flag Register
328
RFC Ch.n Interrupt Enable Register
328
USB 2.0 FS Device Controller (USB, USBMISC)
329
Overview
329
Input/Output Pins and External Connections
330
List of Input/Output Pins
330
External Connections
330
Clock Settings
331
USB Power Supply
332
Operations
332
Initialization
332
Settings When VBUS Is Disconnected
334
Transaction Control
335
Control Transfer
337
Bulk Transfer/Interrupt Transfer
339
Data Flow Control
340
Auto-Negotiation Function
341
Description by Negotiation Function
343
FIFO Management
346
Snooze
348
Interrupts
349
DMA Transfer Requests
350
Control Registers
350
USB Control Register
350
USB Transceiver Control Register
352
USB Status Register
352
USB Endpoint Control Register
353
USB General-Purpose Endpoint FIFO Clear Register
353
USB FIFO Read Cycle Setup Register
354
USB Revision Number Register
354
USB EP0 Setup Data Registers 0-7
354
USB Address Register
355
USB EP0 Configuration Register
355
USB EP0 Maximum Packet Size Register
355
USB EP0 in Transaction Control Register
356
USB EP0 out Transaction Control Register
357
USB Epm Control Registers
358
USB Epm Configuration Registers
359
USB Epm Maximum Packet Size Registers
360
USB Read FIFO Select Register
360
USB Write FIFO Select Register
361
USB FIFO Read/Write Enable Register
361
USB Remaining FIFO Data Count Register
362
USB Remaining FIFO Space Count Register
362
USB Debug RAM Address Register
362
USB Main Interrupt Flag Register
362
USB SIE Interrupt Flag Register
363
USB General-Purpose Endpoint Interrupt Flag Register
364
USB EP0 Interrupt Flag Register
364
USB Main Interrupt Enable Register
366
USB SIE Interrupt Enable Register
366
USB General-Purpose Endpoint Interrupt Enable Register
367
USB EP0 Interrupt Enable Register
367
USB Epm Interrupt Enable Registers
368
USB FIFO Data Register
369
USB Debug RAM Data Register
369
USB Misc Control Register
369
USB FIFO Write DMA Request Enable Register
371
USB FIFO Read DMA Request Enable Register
371
Electrical Characteristics
372
Current Consumption
373
System Reset Controller (SRC) Characteristics
375
Flash Memory Characteristics
377
UART (UART2) Characteristics
380
Synchronous Serial Interface (SPIA) Characteristics
380
C (I2C) Characteristics
383
USB 2.0 FS Device Controller (USB) Characteristics
387
Basic External Connection Diagram
388
Package
390
System Register (SYS)
391
Power Generator (PWGA)
391
Clock Generator (CLG)
391
0X4000 0080
392
Cache Controller (CACHE)
392
0X4000 00A0-0X4000 00A4
392
Watchdog Timer (WDT2)
392
0X4000 00C0-0X4000 00D2
393
0X4000 0100-0X4000 0106
394
0X4000 0160-0X4000 016C
395
0X4000 01B0
395
0X4000 0200-0X4000 02E2
395
0X4000 0300-0X4000 031E
401
0X4000 0380-0X4000 0392
402
0X4000 03A0-0X4000 03Ac
403
0X4000 03B0-0X4000 03Be
404
0X4000 03C0-0X4000 03D6
405
0X4000 0400-0X4000 041C
406
0X4000 0440-0X4000 045C
407
0X4000 0480-0X4000 048C
409
0X4000 0600-0X4000 0612
409
0X4000 0680-0X4000 068C
411
0X4000 0690-0X4000 06A8
411
0X4000 06C0-0X4000 06D6
412
0X4000 0700-0X4000 070C
414
Sound Generator (SNDA)
414
IR Remote Controller (REMC2)
414
0X4000 0800-0X4000 0812
415
0X4000 0840-0X4000 0850
416
0X2040 0000-0X2040 0104, 0X4000 0970-0X4000 0976
417
0X4000 1000-0X4000 2014
423
Appendix B Power Saving
425
Operating Status Configuration Examples for Power Saving
425
Other Power Saving Methods
426
Appendix D Measures against Noise
429
Revision History
430

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User Manuals: Epson S1C31W74 32-Bit Microcontroller

Epson S1C31W74 Technical Manual (434 pages)

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