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ADC12A Ch.n Configuration Register
Register name
Bit
ADC12A_nCFG
15–8
7–2
1–0
Note:
Make sure that the ADC12A_nCTL.BSYSTAT bit is set to 0 before altering the ADC12A_nCFG register.
Bits 15–2
Reserved
Bits 1–0
VRANGE[1:0]
These bits set the A/D converter operating voltage range.
Table 19.7.4 A/D Converter Operating Voltage Range Setting
ADC12A_nCFG.VRANGE[1:0] bits
Notes:
A/D conversion will not be performed if the ADC12_nCFG.VRANGE[1:0] bits = 0x0. Setthese bits to the
value according to the operating voltage to perform A/D conversion.
Be aware that ADC circuit current I
than 0x0 when the ADC12_nCTL.BSYSTAT bit = 1.
ADC12A Ch.n Interrupt Flag Register
Register name
Bit
ADC12A_nINTF
15–9
8
7
6
5
4
3
2
1
0
Bits 15–9
Reserved
Bit 8
OVIF
Bits 7–0
ADmIF
These bits indicate the ADC12A interrupt cause occurrence status.
1 (R): Cause of interrupt occurred
0 (R): No cause of interrupt occurred
1 (W): Clear flag
0 (W): Ineffective
The following shows the correspondence between the bit and interrupt:
ADC12A_nINTF.OVIF bit:
ADC12A_nINTF.ADmCIF bit: Analog input signal m A/D conversion completion interrupt
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Bit name
Initial
–
0x00
–
0x00
VRANGE[1:0]
0x0
0x3
0x2
0x1
0x0
flows if the ADC12_nCFG.VRANGE[1:0] bits are set to a value other
ADC
Bit name
Initial
–
0x00
OVIF
0
AD7IF
0
AD6IF
0
AD5IF
0
AD4IF
0
AD3IF
0
AD2IF
0
AD1IF
0
AD0IF
0
A/D conversion result overwrite error interrupt
Seiko Epson Corporation
Reset
R/W
–
R
–
R
H0
R/W
A/D converter operating voltage range
1.8 to 5.5 V
3.6 to 5.5 V
4.8 to 5.5 V
Conversion disabled
Reset
R/W
–
R
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
Remarks
–
Remarks
–
Cleared by writing 1.
19-11
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