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2.5. Interrupts
CLG has a function to generate the interrupts shown in Table 2.5.1.
Interrupt
IOSC oscillation stabiliza-
tion waiting completion
OSC1 oscillation stabili-
zation waiting completion
OSC3 oscillation stabili-
zation waiting completion
OSC3 oscillation auto-
trimming error
OSC1 oscillation stop
OSC3 oscillation auto-
trimming completion
CLG provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is
sent to the CPU core only when the interrupt flag, of which interrupt has been enabled by the
interrupt enable bit, is set. For more information on interrupt control, refer to the "Interrupt" chapter.
2-20
Table 2.5.1 CLG Interrupt Functions
Interrupt flag
CLGINTF.IOSCSTAIF
When the IOSC oscillation stabilization waiting
operation has completed after the oscillation
starts
CLGINTF.OSC1STAIF
When the OSC1 oscillation stabilization waiting
operation has completed after the oscillation
starts
CLGINTF.OSC3STAIF
When the OSC3 oscillation stabilization waiting
operation has completed after the oscillation
starts
CLGINTF.OSC3TERIF
When the OSC3 oscillation auto-trimming
operation has terminated due to an error
CLGINTF.OSC1STPIF
When OSC1CLK is stopped, or when the
CLGOSC. OSC1EN or CLGOSC1.OSDEN bit
setting is altered from 1 to 0.
CLGINTF.OSC3TEDIF
When the OSC3 oscillation auto-trimming
operation has completed
Seiko Epson Corporation
Set condition
S1C31D50 TECHNICAL MANUAL
Clear
Writing 1
conditio
n
Writing 1
Writing 1
Writing 1
Writing 1
Writing 1
(Rev. 1.00)
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