Advertisement
7.7. Control Register and Port Function Configuration of this IC
This section shows the PPORT control register/bit configuration in this IC and the list of peripheral
I/O functions selectable for each port.
7.7.1. P0 Port Group
The P0 port group supports the GPIO and interrupt functions.
Register name
Bit
PPORTP0DAT
15–8
(P0 Port Data
7–0
Register)
PPORTP0IOEN
15–8
(P0 Port Enable
7–0
Register)
PPORTP0RCTL
15–8
(P0 Port Pull-
7–0
up/down Control
PPORTP0INTF
Register)
15–8
(P0 Port Interrupt
7–0
Flag Register)
PPORTP0INTCTL
15–8
(P0 Port Interrupt
7–0
Control Register)
PPORTP0CHATEN
15–8
(P0 Port Chattering
7–0
Filter Enable
PPORTP0MODSEL
Register)
15–8
(P0 Port Mode
7–0
Select Register)
PPORTP0FNCSEL
15–14
(P0 Port Function
13–12
Select Register)
11–10
9–8
7–6
5–4
3–2
1–0
P0SELy = 0
Port
P0yMUX = 0x0
name
GPIO
Peripheral
P00
P00
P01
P01
P02
P02
P03
P03
P04
P04
P05
P05
P06
P06
P07
P07
*1: Refer to the "Universal Port Multiplexer" chapter.
7-14
Table 7.7.1.1 Control Registers for P0 Port Group
Bit name
Initial
P0OUT[7:0]
0x00
P0IN[7:0]
0x00
P0IEN[7:0]
0x00
P0OEN[7:0]
0x00
P0PDPU[7:0]
0x00
P0REN[7:0]
0x00
–
0x00
P0IF[7:0]
0x00
P0EDGE[7:0]
0x00
P0IE[7:0]
0x00
–
0x00
P0CHATEN[7:0]
0x00
–
0x00
P0SEL[7:0]
0x00
P07MUX[1:0]
0x0
P06MUX[1:0]
0x0
P05MUX[1:0]
0x0
P04MUX[1:0]
0x0
P03MUX[1:0]
0x0
P02MUX[1:0]
0x0
P01MUX[1:0]
0x0
P00MUX[1:0]
0x0
Table 7.7.1.2 P0 Port Group Function Assignment
P0yMUX = 0x1
(Function 0)
(Function 1)
Pin
Peripheral
–
–
UPMUX
UPMUX
–
–
UPMUX
–
–
UPMUX
–
–
UPMUX
–
–
UPMUX
–
–
UPMUX
–
–
UPMUX
–
–
Seiko Epson Corporation
Reset
R/W
H0
R/W
H0
R
H0
R/W
H0
R/W
H0
R/W
H0
R/W
–
R
H0
R/W
Cleared by writing 1.
H0
R/W
H0
R/W
–
R
H0
R/W
–
R
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
P0SELy = 1
P0yMUX = 0x2
(Function 2)
Pin
Peripheral
Pin
*1
–
–
*1
–
–
*1
–
–
*1
–
–
*1
–
–
*1
–
–
*1
–
–
*1
–
–
Remarks
–
–
–
–
–
–
–
–
P0yMUX = 0x3
(Function 3)
Peripheral
Pin
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Advertisement
