Epson S1C31D50 Technical Instructions page 65

5. Interrupt
5.1. Overview
This IC includes a nested vectored interrupt controller (NVIC). For detailed information on the NVIC,
refer to the "Cortex -M0+ Technical Reference Manual."
®
Figure 5.1.1 shows the configuration of the interrupt system.
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Clock
Generator
HALT/SLEEP
cancelation signal
CPU core
IRQ
0
NVIC
IRQ
n
NMI
Figure 5.1.1 Configuration of Interrupt System
Seiko Epson Corporation
Peripheral circuit
Interrupt request
Peripheral circuit
Interrupt request
Watchdog timer
5-1