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DMAC Error Interrupt Flag Register
Register name
Bit
DMACERRIF
31–24
23–16
15–8
7–1
0
Bits 31–1
Reserved
Bit 0
ERRIF
This bit indicates the DMAC error interrupt cause occurrence status.
1 (R): Cause of interrupt occurred
0 (R): No cause of interrupt occurred
1 (W): Clear flag
0 (W): Ineffective
DMAC Transfer Completion Interrupt Flag Register
Register name
Bit
DMACENDIF
31–0
Bits 31–0
ENDIF[31:0]
These bits indicate the DMA transfer completion interrupt cause occurrence status of
each DMAC channel.
1 (R): Cause of interrupt occurred
0 (R): No cause of interrupt occurred
1 (W): Clear flag
0 (W): Ineffective
Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented
channels are ineffective.
DMAC Transfer Completion Interrupt Enable Set Register
Register name
Bit
DMACENDIESET
31–0
Bits 31–0
ENDIESET[31:0]
These bits enable DMA transfer completion interrupts to be generated from each DMAC
channel.
1 (W): Enable interrupt
0 (W): Ineffective
1 (R): Interrupt has been enabled.
0 (R): Interrupt has been disabled.
Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented
channels are ineffective.
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Bit name
Initial
–
0x00
–
0x00
–
0x00
–
0x00
ERRIF
0
Bit name
Initial
ENDIF[31:0]
0x0000
0000
Bit name
Initial
ENDIESET[31:0]
0x0000
0000
Seiko Epson Corporation
Reset
R/W
–
R
–
R
–
R
–
R
H0
R/W
Cleared by writing 1.
Reset
R/W
H0
R/W
Cleared by writing 1.
Reset
R/W
H0
R/W
Remarks
–
Remarks
Remarks
–
6-17
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