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19.3.2. Sampling Time
The ADC12A includes a sample and hold circuit. The sampling time must be set so that it will satisfy the
time required for acquiring input voltage (t
circuit of the analog input portion.
R
For the R
and C
ADIN
ADIN
in the "Electrical Characteristics" chapter. Based on these values, configure the ADC12A operating
clock CLK_T16_k and the ADC12A_nTRG.SMPCLK[2:0] bits that set the sampling time so that these
settings will satisfy the equations shown below.
tACQ = 8 × (RS + RADIN) × CADIN
1
× SMPCLK > ��
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Where
fCLK_ADC: CLK_T16_k frequency [Hz]
SMPCLK: Sampling time = ADC12A_nTRG.SMPCLK[2:0] bit-setting (4 to 11 CLK_T16_k cycles)
The following shows the relationship between the sampling time and the maximum sampling rate.
Maximum sampling rate [sps] =
19.4. Operations
19.4.1. Initialization
The ADC12A should be initialized with the procedure shown below.
1. Assign the ADC12A input function to the ports. (Refer to the "I/O Ports" chapter.)
2. Configure the 16-bit timer Ch.k operating clock so that it will satisfy the sampling time.
3. Set the ADC12A_nCTL.MODEN bit to 1.
4. Configure the following ADC12A_nTRG register bits:
ADC12A_nTRG.SMPCLK[2:0] bits
-
ADC12A_nTRG.CNVTRG[1:0] bits
-
ADC12A_nTRG.CNVMD bit
-
ADC12A_nTRG.STMD bit
-
ADC12A_nTRG.STAAIN[2:0] bits
-
ADC12A_nTRG.ENDAIN[2:0] bits
-
5. Set the ADC12A_nCFG.VRANGE[1:0] bits.
6. Set the following bits when using the interrupt:
Write 1 to the interrupt flags in the ADC12A_nINTF register.
-
Set the interrupt enable bits in the ADC12A_nINTE register to 1. (Enable interrupts)
-
7. Configure the DMA controller and set the following ADC12A control bit when using DMA transfer:
Write 1 to the DMA transfer request enable bit in the ADC12A_nDMAEN register. (Enable DMA
-
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
: acquisition time). Figure 19.3.2.1 shows an equivalent
ACQ
VDD
ADINnm
S
VSS
Figure 19.3.2.1 Equivalent Circuit of Analog Input Portion
values in the equivalent circuit, refer to "12-bit A/D Converter Characteristics"
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ADC
SMPCLK + 13
Seiko Epson Corporation
VDD
CADIN
R
: Source impedance
S
RADIN: Analog input resistance
CADIN: Analog input capacitance
VSS
(����. 19.1)
(����. 19.2)
(����. 19.3)
(Enable ADC12A operations)
(Set sampling time)
(Select conversion start trigger source)
(Set conversion mode)
(Set data storing mode)
(Set analog input pin to be A/D converted first)
(Set analog input pin to be A/D converted last)
(Set operating voltage range according to V
(Clear interrupt flags)
)
DD
19-3
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