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13.2.3.
Input Pin Pull-Up Function _______________________________________________ 13-3
13.2.4.
Output Pin Open-Drain Output Function____________________________________ 13-3
13.2.5.
Input/Output Signal Inverting Function _____________________________________ 13-3
13.3.
Clock Settings ___________________________________________________ 13-4
13.3.1.
UART3 Operating Clock _________________________________________________ 13-4
13.3.2.
Clock Supply in SLEEP Mode ______________________________________________ 13-4
13.3.3.
Clock Supply During Debugging ___________________________________________ 13-4
13.3.4.
Baud Rate Generator ___________________________________________________ 13-4
13.4.
Data Format ____________________________________________________ 13-5
13.5.
Operations ______________________________________________________ 13-6
13.5.1.
Initialization __________________________________________________________ 13-6
13.5.2.
Data Transmission ______________________________________________________ 13-6
13.5.3.
Data Reception ________________________________________________________ 13-8
13.5.4.
IrDA Interface _________________________________________________________ 13-9
13.5.5.
Carrier Modulation____________________________________________________ 13-10
13.6.
Receive Errors __________________________________________________ 13-11
13.6.1.
Framing Error ________________________________________________________ 13-11
13.6.2.
Parity Error __________________________________________________________ 13-11
13.6.3.
Overrun Error ________________________________________________________ 13-11
13.7.
Interrupts _____________________________________________________ 13-12
13.8.
DMA Transfer Requests ___________________________________________ 13-12
13.9.
Control Registers ________________________________________________ 13-13
14.
Synchronous Serial Interface (SPIA) ________________________________ 14-1
14.1.
Overview _______________________________________________________ 14-1
14.2.
Input/Output Pins and External Connections __________________________ 14-2
14.2.1.
List of Input/Output Pins ________________________________________________ 14-2
14.2.2.
External Connections ___________________________________________________ 14-2
14.2.3.
Pin Functions in Master Mode and Slave Mode ______________________________ 14-3
14.2.4.
Input Pin Pull-Up/Pull-Down Function _____________________________________ 14-3
14.3.
Clock Settings ___________________________________________________ 14-4
14.3.1.
SPIA Operating Clock ___________________________________________________ 14-4
14.3.2.
Clock Supply During Debugging ___________________________________________ 14-5
SPI Clock (SPICLK n ) Phase and Polarity _____________________________________ 14-5
14.3.3.
14.4.
Data Format ____________________________________________________ 14-5
14.5.
Operations ______________________________________________________ 14-6
14.5.1.
Initialization __________________________________________________________ 14-6
14.5.2.
Data Transmission in Master Mode ________________________________________ 14-6
14.5.3.
Data Reception in Master Mode__________________________________________ 14-9
14.5.4.
Terminating Data Transfer in Master Mode ________________________________ 14-11
14.5.5.
Data Transfer in Slave Mode ____________________________________________ 14-11
14.5.6.
Terminating Data Transfer in Slave Mode __________________________________ 14-12
14.6.
Interrupts _____________________________________________________ 14-13
14.7.
DMA Transfer Requests ___________________________________________ 14-14
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Seiko Epson Corporation
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