Epson S1C31D50 Technical Instructions page 438

0x0020 1000–0x0020 2014
Address Register name
DMACSTAT
0x0020 (DMAC Status
1000 Register)
DMACCFG
0x0020
(DMAC
1004
Configuration
Register)
DMACCPTR
0x0020 (DMAC Control
1008 Data Base
Pointer Register)
DMACACPTR
(DMAC Alternate
0x0020
Control Data
100c
Base Pointer
Register)
DMACSWREQ
0x0020
(DMAC Software
1014
Request Register)
DMACRMSET
0x0020 (DMAC Request
1020 Mask Set
Register)
DMACRMCLR
0x0020 (DMAC Request
1024 Mask Clear
Register)
DMACENSET
0x0020
(DMAC Enable
1028
Set Register)
DMACENCLR
0x0020
(DMAC Enable
102c
Clear Register)
B-60
DMA Controller (DMAC)
Bit Bit name
31–24 –
23–21 –
20–16 CHNLS[4:0]
15–8 –
7–4 STATE[3:0]
3–1 –
0 MSTENSTAT
31–24 –
23–16 –
15–8 –
7–1 –
0 MSTEN
31–7 CPTR[31:7]
6–0 CPTR[6:0]
31–0 ACPTR[31:0]
31–24 –
23–16 –
15–8 –
7–4 –
3–0 SWREQ[3:0]
31–24 –
23–16 –
15–8 –
7–4 –
3–0 RMSET[3:0]
31–24 –
23–16 –
15–8 –
7–4 –
3–0 RMCLR[3:0]
31–24 –
23–16 –
15–8 –
7–4 –
3–0 ENSET[3:0]
31–24 –
23–16 –
15–8 –
7–4 –
3–0 ENCLR[3:0]
Seiko Epson Corporation
Initial Reset R/W
0x00 – R
0x0 – R
* H0 R
0x00 – R
0x0 H0 R
0x0 – R
0 H0 R
0x00 – R
0x00 – R
0x00 – R
0x00 – R
– – W
0x000
H0 R/W
0
0x00 H0 R
– H0 R
– – R
– – R
– – R
– – R
– – W
0x00 – R
0x00 – R
0x00 – R
0x0 – R
0x0 H0 R/W
– – R
– – R
– – R
– – R
– – W
0x00 – R
0x00 – R
0x00 – R
0x0 – R
0x0 H0 R/W
– – R
– – R
– – R
– – R
– – W
S1C31D50 TECHNICAL MANUAL
Remarks
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* Number of channels
implemented - 1
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(Rev. 1.00)