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16.4.3. Data Reception in Master Mode
A data receiving procedure in master mode and the I2C Ch.n operations are shown below. Figures
16.4.3.1 and show an operation example and a flowchart, respectively.
Data receiving procedure
1. Issue a START condition by setting the I2C_nCTL.TXSTART bit to 1.
2. Wait for a transmit buffer empty interrupt (I2C_nINTF.TBEIF bit = 1) or a START condition interrupt
(I2C_nINTF.STARTIF bit = 1).
Clear the I2C_nINTF.STARTIF bit by writing 1 after the interrupt has occurred.
3. Write the 7-bit slave address to the I2C_nTXD.TXD[7:1] bits and 1 that represents READ as the data
transfer direction to the I2C_nTXD.TXD0 bit.
4. (When DMA is used) Configure the DMA controller and set a DMA transfer request enable bit in
the I2C_ nRBFDMAEN register to 1 (DMA transfer request enabled). (This automates the data
receiving procedure Steps 5, 7, and 9.)
5. (When DMA is not used) Wait for a receive buffer full interrupt (I2C_nINTF.RBFIF bit = 1)
generated when a one-byte reception has completed.
6. Perform one of the operations below when the last or next-to-last data is received.
When the next-to-last data is received, write 1 to the I2C_nCTL.TXNACK bit to send a NACK
i.
after the last data is received, and then go to Step 7.
When the last data is received, read the received data from the I2C_nRXD register and set
ii.
the I2C_nCTL.TXSTOP to 1 to generate a STOP condition. Then go to Step 10.
7. (When DMA is not used) Read the received data from the I2C_nRXD register.
8. 8．If a NACK reception interrupt (I2C_nINTF.NACKIF bit = 1) has occurred, clear the
I2C_nINTF.NACKIF bit and issue a STOP condition by setting the I2C_nCTL.TXSTOP bit to 1. Then
go to Step 10 or Step 1 if making a retry.
9. (When DMA is not used) Repeat Steps 5 to 7 until the end of data reception.
10. Wait for a STOP condition interrupt (I2C_nINTF.STOPIF bit = 1).
Clear the I2C_nINTF.STOPIF bit by writing 1 after the interrupt has occurred.
Data receiving operations
Generating a START condition
It is the same as the data transmission in master mode.
Sending slave address
It is the same as the data transmission in master mode. Note, however, that the I2C_nTXD.TXD0
bit must be set to 1 that represents READ as the data transfer direction to issue a request to the
slave to send data.
Receiving data
After the slave address has been sent, the slave device sends an ACK and the first data. The I2C
Ch.n sets the I2C_nINTF.RBFIF bit to 1 after the data reception has completed. Furthermore, the
I2C Ch.n returns an ACK. To return a NACK, such as for a response after the last data has been
received, write 1 to the I2C_ nCTL.TXNACK bit before the I2C_nINTF.RBFIF bit is set to 1.
The received data can be read out from the I2C_nRXD register after a receive buffer full interrupt
has occurred. The I2C Ch.n pulls down SCL to low and enters standby state until data is read out
from the I2C_ nRXD register.
This reading triggers the I2C Ch.n to start subsequent data reception.
16-8
Seiko Epson Corporation
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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