Advertisement
4.8. Control Registers
System Protect Register
Register name
Bit
SYSPROT
15–0
Bits 15–0
PROT[15:0]
These bits protect the control registers related to the system against writings.
0x0096 (R/W):
Other than 0x0096 (R/W):
While the system protection is enabled, any data will not be written to the affected
control bits (bits with "WP" or "R/WP" appearing in the R/W column).
CACHE Control Register
Register name
Bit
CACHECTL
15–8
7–2
1
0
Bits 15–1 Reserved
Bit 0
CACHEEN
This bit enables the instruction cache function.
1 (R/W): Enable instruction cache
0 (R/W): Disable instruction cache
FLASHC Flash Read Cycle Register
Register name
Bit
FLASHCWAIT
15–9
8
7–2
1–0
Bits 15–2
Reserved
Bits 1–0
RDWAIT[1:0]
These bits set the number of bus access cycles for reading from the Flash memory.
Table 4.8.1 Setting Number of Bus Access Cycles for Flash Read
FLASHCWAIT.
RDWAIT[1:0] bits
0x3
0x2
0x1
0x0
Note:
Be sure to set the FLASHCWAIT.RDWAIT[1:0] bits before the system clock is configured.
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Bit name
Initial
PROT[15:0]
0x0000
Disable system protection
Enable system protection
Bit name
Initial
–
0x00
–
0x00
reserved
1
CACHEEN
0
Bit name
Initial
–
0x00
(reserved)
0
–
0x00
RDWAIT[1:0]
0x1
Number of bus
access cycles
4
3
2
1
Seiko Epson Corporation
Reset
R/W
H0
R/W
Reset
R/W
–
R
–
R
–
R
H0
R/W
Reset
R/W
–
R
H0
R/WP
–
R
H0
R/WP
System clock frequency
PWGACTL.
REGSEL bit = 0
REGSEL bit = 1
2.1 MHz (max.)
16.6 MHz (max.)
1.05 MHz (max.)
8.4 MHz (max.)
Remarks
–
Remarks
–
Remarks
–
PWGACTL.
4-5
Advertisement
