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Epson S1C17F13 Technical Manual

Epson S1C17F13 Technical Manual

Cmos 16-bit single chip microcontroller
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CMOS 16-BIT SINGLE CHIP MICROCONTROLLER
S1C17F13
Technical Manual
Rev. 1.0

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Summary of Contents for Epson S1C17F13

  • Page 1 CMOS 16-BIT SINGLE CHIP MICROCONTROLLER S1C17F13 Technical Manual Rev. 1.0...
  • Page 2 No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability...

  • Page 3: Configuration Of Product Number

    Tx : A socket for mounting Cx : Compiler package Sx : Middleware package Yx : Writer software Corresponding model number 17xxx: for S1C17xxx Tool classification C: microcomputer use Product classification S5U1: development tool for semiconductor products Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 4: Preface

    PREFACE Preface This is a technical manual for designers and programmers who develop a product using the S1C17F13. This document describes the functions of the IC, embedded peripheral circuit operations, and their control methods. For the CPU functions and instructions, refer to the “S1C17 Family S1C17 Core Manual.” For the functions and operations of the debugging tools, refer to the respective tool manuals.

  • Page 5: Table Of Contents

    3.1 Overview ......................... 3-1 3.2 CPU Core ........................3-2 3.2.1 CPU Registers ....................3-2 3.2.2 Instruction Set ....................3-2 3.2.3 Reading PSR ....................3-2 3.2.4 I/O Area Reserved for the S1C17 Core ............3-2 Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)
  • Page 6 6.2.4 CMOS Output and High Impedance State ............6-3 6.3 Clock Settings ......................... 6-3 6.3.1 PPORT Operating Clock ................... 6-3 6.3.2 Clock Supply in SLEEP Mode ................6-3 6.3.3 Clock Supply in DEBUG Mode ................. 6-3 Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)
  • Page 7 8.5 SVD Interrupt and Reset ....................8-4 8.5.1 SVD Interrupt ....................8-4 8.5.2 SVD Reset ......................8-5 8.6 Control Registers ......................8-5 SVD Clock Control Register ...................... 8-5 SVD Control Register ........................ 8-6 Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)
  • Page 8 10.6.3 Overrun Error ....................10-8 10.7 Interrupts ........................10-8 10.8 Control Registers ......................10-8 UART Ch.n Clock Control Register ..................10-8 UART Ch.n Mode Register ....................... 10-9 UART Ch.n Baud–Rate Register ..................... 10-10 Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)
  • Page 9 12.4.6 Data Reception in Slave Mode ..............12-12 12.4.7 Slave Operations in 10-bit Address Mode ............ 12-14 12.4.8 Automatic Bus Clearing Operation ............... 12-14 12.4.9 Error Detection ....................12-15 12.5 Interrupts ........................12-16 Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)
  • Page 10 16.3 Clock Settings ......................16-2 16.3.1 T16A3 Operating Clock ................. 16-2 16.3.2 Clock Supply in SLEEP Mode ............... 16-3 16.3.3 Clock Supply in DEBUG Mode ..............16-3 16.3.4 Event Counter Clock ..................16-3 Seiko epson Corporation viii S1C17F13 TeChniCal Manual (Rev. 1.0)
  • Page 11 19.2.2 External Connections ..................19-2 19.3 Clock Settings ......................19-3 19.3.1 RFC Operating Clock ..................19-3 19.3.2 Clock Supply in SLEEP Mode ............... 19-3 19.3.3 Clock Supply in DEBUG Mode ..............19-3 Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)
  • Page 12 22.6 Flash Memory Characteristics ..................22-6 22.7 Input/Output Port (PPORT) Characteristics ..............22-7 22.8 Supply Voltage Detector (SVD) Characteristics ............22-8 22.9 UART (UART) Characteristics ..................22-9 22.10 Synchronous Serial Interface (SPIA) Characteristics ..........22-9 Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)
  • Page 13 B.1 Operating Status Configuration Examples for Power Saving ........AP-B-1 B.2 Other Power Saving Methods ..................AP-B-2 Appendix C Mounting Precautions ................AP-C-1 Appendix D Measures Against Noise ................ AP-D-1 Appendix E Initialization Routine ................AP-E-1 Revision History Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 14: Overview

    1 OVERVIEW Overview The S1C17F13 is an ultra low-power MCU equipped with a display memory and an EPD timing controller to send display data for using the active EPD panels. This IC includes the synchronous serial interface, parallel interface, UART, and I C to communicate with an EPD panel and other devices.
  • Page 15 *1 When using the EPD timing controller (EPD Tcon), an area for storing the timing parameters must be allocated in the Flash memory. When using the internal Flash voltage booster as the Flash programing power supply, an area for storing the control program must be allocated in the Flash memory. Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 16: Block Diagram

    RFCLKO0–1 16-bit timer Temperature (T16) detection circuit Ch.0–3 VM1–2 (TEM) 16-bit PWM timer EXCL0–1 (T16A3) TOUTA0/CAPA0–1 Ch.0–1 Power generator TOUTB0/CAPB0–1 (PWG) UART USIN0 (UART) USOUT0 IREF_M Figure 1. 2.1 S1C17F13 Block Diagram Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 17: Pins

    Port function or signal assignment Pin name P14/SENB1/PIOD0 P15/SENA1/PIOD1 P16/REF1/PIOD2 P07/SDO0/PIOA3 P17/RFIN1/PIOD3 P06/SDI0/PIOA2 P05/SPICLK0/PIOA1 P20/SDO1/PIOD4 P04/#SPISS0/PIOA0 P21/SDI1/PIOD5 P03/EXOSC/#PIOCE P22/SPICLK1/PIOD6 P02/EXCL0/#PIORD P23/#SPISS1/PIOD7 P24/#SPISS2 P25/SPICLK2 P26/SDI2 P27/SDO2 P30/EXCL1/RFCLKO0 Figure 1. 3.1.1 S1C17F13 Pin Configuration Diagram (TQFP13-64pin) Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 18: Pad Configuration Diagram (Chip)

    – N.C. Die No. CJF13Dxxx 3.339 mm Figure 1. 3.2.1 S1C17F13 Pad Configuration Diagram (Chip) Pad opening No. 1–21, 39–57: X = 76 µm, Y = 90 µm No. 22–29: X = 85 µm, Y = 122 µm No. 30–38, 58–78: X = 90 µm, Y = 76 µm Chip thickness 400 µm...

  • Page 19: Pin Descriptions

    Temperature sensor voltage monitor pin (Leave the pin open during normal operation.) – – Temperature sensor voltage monitor pin (Leave the pin open during normal operation.) OSC1 OSC1 – – OSC1A oscillator circuit input Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)
  • Page 20 – General-purpose I/O port RFIN1 R/F converter Ch.1 oscillation input PIOD3 Parallel interface data input/output Hi-Z General-purpose I/O port ✓ SDO1 Synchronous serial interface Ch.1 data output PIOD4 Parallel interface data input/output Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)
  • Page 21 On-chip debugger data input/output ✓ General-purpose I/O port DCLK O (H) On-chip debugger clock output ✓ General-purpose I/O port Note: In the peripheral circuit descriptions, the assigned signal name is used as the pin name. Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 22: Power Supply, Reset, And Clocks

    • Embedded voltage booster for generating the Flash erasing/programming voltage Figure 2.1.1.1 shows the PWG configuration. VD1ECO Internal logic and high-speed oscillator circuits regulator Low-speed regulator oscillator circuit Flash voltage Flash memory booster Figure 2. 1.1.1 PWG Configuration Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 23: Pins

    • Embedded reset hold circuit maintains reset state to boot the system safely while the internal power supply is un- stable after power on or the oscillation frequency is unstable after the clock source is initiated. Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 24: Input Pin

    Figure 2.2.3.1 shows an example of POR and BOR internal reset operation according to variations in V Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 25: Initialization Conditions (Reset Groups)

    POR and BOR Peripheral circuit software reset Reset state is canceled immediately (MODEN and SFTRST bits. The after the reset request is canceled. software reset operations de- pend on the peripheral circuit. Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 26: Clock Generator (Clg)

    EXOSC EXOSC EXOSCCLK clock input circuit FOUTEN Peripheral circuit 1 FOUT EXOSC Clock clock input CLKSRC[x:0] selector circuit CLKDIV[x:0] FOUTDIV[2:0] Peripheral circuit n Clock CLKSRC[x:0] selector CLKDIV[x:0] Figure 2. 3.1.1 CLG Configuration Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 27: Input/Output Pins

    The embedded gain-controlled oscillation inverter allows selection of the resonator from a wide frequency range. For the recommended parts and the oscillation characteristics, refer to the “Basic External Connection Diagram” chapter and “OSC3A oscillator circuit characteristics” in the “Electrical Characteristics” chapter, respectively. Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)
  • Page 28 EXOSC has no oscillation stabilization waiting circuit included, therefore, it must be enabled when a stabilized clock is being supplied. For the input clock characteristics, refer to “EXOSC external clock input characteris- tics” in the “Electrical Characteristics” chapter. Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 29: Operations

    3. Write 0x0096 to the MSCPROT.PROT[15:0] bits. (Remove system protection) 4. Configure the following CLGOSC3A register bits according to the resonator used. - CLGOSC3A.INVN[1:0] bits (Set oscillation inverter gain) - CLGOSC3A.OSC3AWT[1:0] bits (Set oscillation stabilization waiting time) Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)
  • Page 30 SLEEP mode and RUN mode, and the peripheral circuits to continue operating without disabling the clock in SLEEP mode. The CLGOSC.OSC3BSLPC, CLGOSC.OSC1SLPC, CLGOSC.OSC3ASLPC, and CLGOSC.EXOSCSLPC bits are used for this control. Figure 2.3.4.2 shows a control example. Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)
  • Page 31 2. Configure the following CLGFOUT register bits: - CLGFOUT.FOUTSRC[1:0] bits (Select clock source) - CLGFOUT.FOUTDIV[2:0] bits (Set clock division ratio) - Set the CLGFOUT.FOUTEN bit to 1. (Enable clock external output) Seiko epson Corporation 2-10 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 32: Operating Mode

    When a debug interrupt occurs, the CPU enters DEBUG mode. DEBUG mode is canceled when the retd in- struction is executed. For more information on DEBUG mode, refer to “Debugger” in the “CPU and Debugger” chapter. Seiko epson Corporation S1C17F13 TeChniCal Manual 2-11 (Rev. 1.0)

  • Page 33: Interrupts

    OSC1STAIF eration has completed after the oscillation starts OSC3A oscillation stabilization CLGINTF. When the OSC3A oscillation stabilization waiting Writing 1 waiting completion OSC3ASTAIF operation has completed after the oscillation starts Seiko epson Corporation 2-12 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 34: Control Registers

    CLGOSC.****SLPC bit retains 1 after a wake-up. Bit 14 Reserved Bits 13–12 WuPDiV[1:0] These bits select the SYSCLK division ratio for resetting the CLGSCLK.CLKDIV[1:0] bits at wake-up. This setting is ineffective when the CLGSCLK.WUPMD bit = 0. Seiko epson Corporation S1C17F13 TeChniCal Manual 2-13 (Rev. 1.0)

  • Page 35: Clg Oscillation Control Register

    Bit 9 OSC1SlPC Bit 8 OSC3BSlPC These bits control the clock source operations in SLEEP mode. 1 (R/W): Stop clock source in SLEEP mode 0 (R/W): Continue operation state before SLEEP Seiko epson Corporation 2-14 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 36: Clg Osc3B Control Register

    This bit selects the OSC1 clock source. 1 (R/WP): OSC1B oscillator circuit 0 (R/WP): OSC1A oscillator circuit Bits 1–0 OSC1WT[1:0] These bits set the oscillation stabilization waiting time for the OSC1 oscillator circuit. Seiko epson Corporation S1C17F13 TeChniCal Manual 2-15 (Rev. 1.0)

  • Page 37: Clg Osc3A Control Register

    These bits indicate the oscillation stabilization waiting completion interrupt cause occurrence status in each clock source. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective Seiko epson Corporation 2-16 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 38: Clg Interrupt Enable Register

    6.8 FOUT Clock Source and Division Ratio Settings CLGFOUT.FOUTSRC[1:0] bits CLGFOUT. FOUTDIV[2:0] bits OSC3BCLK OSC1CLK OSC3ACLK SYSCLK 1/128 1/32,768 1/128 Reserved 1/64 1/4,096 1/64 Reserved 1/32 1/1,024 1/32 Reserved 1/16 1/256 1/16 Reserved Reserved Reserved Reserved Seiko epson Corporation S1C17F13 TeChniCal Manual 2-17 (Rev. 1.0)
  • Page 39 0 (R/W): Disable external output Note: Since the FOUT signal generated is out of sync with writings to the CLGFOUT.FOUTEN bit, a glitch may occur when the FOUT output is enabled or disabled. Seiko epson Corporation 2-18 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 40: Cpu And Debugger

    3 CPU AND DEBUGGER CPU and Debugger Overview This IC incorporates the Seiko Epson original 16-bit CPU core (S1C17) with a debugger. The main features of the CPU core are listed below. • Seiko Epson original 16-bit RISC processor - 24-bit general-purpose registers: 8...

  • Page 41: Cpu Core

    Debugging requires a 64-byte debugging work area. For more information on the work area location, refer to the “Memory and Bus” chapter. The start address of this debugging work area can be read from the DBRAM register. Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 42: List Of Debugger Input/Output Pins

    The value (0 to 7) of the PSR IL[2:0] (interrupt level) bits can be read out with these bits. Bit 4 PSRie The value (0 or 1) of the PSR IE (interrupt enable) bit can be read out with this bit. Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 43: Debug Ram Base Register

    – 23–0 DBRAM[23:0] *1 Debugging work area start address Bits 31–24 Reserved Bits 23–0 DBRaM[23:0] The start address of the debugging work area (64 bytes) can be read out with these bits. Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 44: Memory And Bus

    Access size designated by the CPU instructions (e.g., ld %rd, [%rb] → 16-bit data transfer) • Access size: Table 4.2.1 lists numbers of bus access cycles by different device size and access size. The peripheral circuits can be accessed with an 8-bit, 16-bit, or 32-bit instruction. Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 45: Flash Memory

    S5U1C17001C Manual.” The IC can also be shipped after being programmed in the factory with the ROM data developed. Should you desire to ship the IC with ROM data programmed from the factory, please contact our cus- tomer support. Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 46: Flash Security Function

    The control registers for the peripheral circuits are located in the 8K-byte area beginning with address 0x4000. Table 4.6.1 shows the control register map. For details of each control register, refer to “List of Peripheral Circuit Registers” in the Appendix or “Control Registers” in each peripheral circuit chapter. Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)
  • Page 47 P1 Port Pull-up/down Control Register 0x4216 P1INTF P1 Port Interrupt Flag Register 0x4218 P1INTCTL P1 Port Interrupt Control Register 0x421a P1CHATEN P1 Port Chattering Filter Enable Register 0x421c P1MODSEL P1 Port Mode Select Register Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 48: Uart Ch.n Control Register

    T16A3 Counter Ch.0 Data Register 0x5006 T16A0CCCTL T16A3 Comparator/Capture Ch.0 Control Register 0x5008 T16A0CCA T16A3 Comparator/Capture Ch.0 A Data Register 0x500a T16A0CCB T16A3 Comparator/Capture Ch.0 B Data Register 0x500c T16A0INTF T16A3 Ch.0 Interrupt Flag Register Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)
  • Page 49 RFC Ch.0 Interrupt Flag Register 0x5450 RFC0INTE RFC Ch.0 Interrupt Enable Register R/F converter (RFC) Ch.1 0x5460 RFC1CLK RFC Ch.1 Clock Control Register 0x5462 RFC1CTL RFC Ch.1 Control Register 0x5464 RFC1TRG RFC Ch.1 Oscillation Trigger Register Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 50: System-Protect Function

    R/WP Always set to 0. – – – 6–4 (reserved) – – – 2–0 IRAMSZ[2:0] R/WP Bits 15–3 Reserved Bits 2–0 iRaMSZ[2:0] These bits set the internal RAM size that can be used. Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 51: Flashc Flash Read Cycle Register

    FLASHCWAIT.RDWAIT[1:0] bits Number of bus access cycles System clock frequency 20.0 MHz (max.) 20.0 MHz (max.) 16.3 MHz (max.) 8.2 MHz (max.) note: Be sure to set the FLASHCWAIT.RDWAIT[1:0] bits before the system clock is configured. Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 52: Interrupt Controller (Itc)

    Address misaligned interrupt Memory access instruction – (0xfffc00) Debugging interrupt brk instruction, etc. 2 (0x02) TTBR + 0x08 Watchdog timer overflow 3 (0x03) TTBR + 0x0c Reserved for C compiler – – Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)
  • Page 53 TTBR + 0x50 R/F Ch.0 converter interrupt • Reference oscillation completion • Sensor A oscillation completion • Sensor B oscillation completion • Measurement counter overflow error • Time base counter overflow error Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 54: Vector Table Base Address (Ttbr)

    ITC if the status is changed to interrupt enabled when the interrupt flag is 1. For specific information on causes of interrupts, interrupt flags, and interrupt enable bits, refer to the respective pe- ripheral circuit descriptions. Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 55: Itc Interrupt Request Processing

    (0–7) to be set to the IL[2:0] bits in the PSR. The software inter- rupt cannot be disabled (non-maskable interrupt). The processor performs the same interrupt processing operation as that of the hardware interrupt. Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 56: Interrupt Processing By The Cpu

    – 2–0 ILVy [2:0] Bits 15–11 Reserved Bits 7–3 Reserved = 2x +1) Bits 10–8 ilVy [2:0] = 2x) Bits 2–0 ilVy [2:0] These bits set the interrupt level of each interrupt. Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)
  • Page 57 R/F converter Ch.0 interrupt (ILVRFC_0) ITCLV9 15–11 – 0x00 – – (ITC Interrupt Level 10–8 ILV19[2:0] Temperature detection circuit interrupt Setup Register 9) (ILVTEM) 7–3 – 0x00 – – 2–0 ILV18[2:0] EPD timing controller interrupt (ILVEPD_Tcon) Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 58: O Ports (Pport)

    PxEDGEy System reset control circuit reset control controller PxINT circuit PxIFy KRSTCFG[1:0] PxIEy Interrupt controller Exist only in the ports that supports the interrupt function. Figure 6. 1.1 PPORT Configuration Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 59: I/O Cell Structure And Functions

    Falling time (port level = high → low) [second] High level Schmitt input threshold voltage [V] Low level Schmitt input threshold voltage [V] : Pull-up/pull-down resistance [W] Pin capacitance [F] Parasitic capacitance on the board [F] BOARD Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 60: Cmos Output And High Impedance State

    • Port pins: High impedance state • Port function: Configured to GPIO This status continues until the ports are configured via software. The debugging function ports are configured for debug signal input/output. Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)
  • Page 61 * Steps 1 and 5 are required for the ports with an interrupt function. Step 2 is required for the ports with a chat- tering filter function. Table 6.4.1.1 lists the port status according to the combination of data input/output control and pull-up/down control. Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 62: Port Input/Output Control

    2. Configure the input pin combination for key-entry reset using the PCLK.KRSTCFG[1:0] bits. Note: When enabling the key-entry reset function, be sure to configure the port pins to be used for it as general-purpose input pins before setting the PCLK.KRSTCFG[1:0] bits. Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 63: Interrupts

    (PxIOEN.PxOENy bit = 0), it does not affect the pin status. These bits do not affect the outputs when the port is used as a peripheral I/O function. Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 64: Px Port Enable Register

    PxIOEN.PxIENy bit is set and the port is not pulled up/down. These bits do not affect the pull-up/down control when the port is used as a peripheral I/O function. Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 65: Px Port Interrupt Flag Register

    PxMODSEL 15–8 – 0x00 – – 7–0 PxSEL[7:0] 0x00 *1: The bit configuration differs depending on the port group. *2: The initial value may be changed by the port. Bits 15–8 Reserved Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 66: Px Port Function Select Register

    Table 6. 6.2 Key-Entry Reset Function Settings PCLK.KRSTCFG[1:0] bits key-entry reset Reset when P0[3:0] inputs = all low Reset when P0[2:0] inputs = all low Reset when P0[1:0] inputs = all low Disable Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 67: P Port Interrupt Flag Group Register

    A port generated an interrupt 0 (R): No port generated an interrupt The PINTFGRP.PxINT bit is cleared when the interrupt flag for the port that has generated an interrupt is cleared. Seiko epson Corporation 6-10 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 68: Control Register And Port Function Configuration Of This Ic

    SPI Ch.0 #SPISS0 PIOA0 – – – – SPI Ch.0 SPICLK0 PIOA1 – – – – SPI Ch.0 SDI0 PIOA2 – – – – SPI Ch.0 SDO0 PIOA3 – – – – Seiko epson Corporation S1C17F13 TeChniCal Manual 6-11 (Rev. 1.0)

  • Page 69: P1 Port Group

    7.3.1 Control Registers for P2 Port Group Register name Bit name Initial Reset Remarks P2DAT 15–8 P2OUT[7:0] 0x00 – (P2 Port Data 7–0 P2IN[7:0] Register) P2IOEN 15–8 P2IEN[7:0] 0x00 – (P2 Port Enable 7–0 P2OEN[7:0] 0x00 Register) Seiko epson Corporation 6-12 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 70: P3 Port Group

    – (P3 Port Pull-up/down 7–0 P3REN[7:0] 0x00 Control Register) P3INTF 15–0 – 0x0000 – – P3INTCTL P3CHATEN P3MODSEL 15–8 – 0x00 – – (P3 Port Mode Select 7–0 P3SEL[7:0] 0x00 Register) Seiko epson Corporation S1C17F13 TeChniCal Manual 6-13 (Rev. 1.0)

  • Page 71: P4 Port Group

    P4yMUX = 0x3 Port name GPIO (Function 0) (Function 1) (Function 2) (Function 3) Peripheral Peripheral Peripheral Peripheral UART USIN0 PIOD2 – – – – UART USOUT0 PIOD3 – – – – Seiko epson Corporation 6-14 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 72: Pd Port Group

    (P Port Clock Control DBRUN R/WP Register) 7–4 CLKDIV[3:0] R/WP 3–2 KRSTCFG[1:0] R/WP 1–0 CLKSRC[1:0] R/WP PINTFGRP 15–8 – 0x00 – – (P Port Interrupt Flag 7–2 – 0x00 – Group Register) P1INT P0INT Seiko epson Corporation S1C17F13 TeChniCal Manual 6-15 (Rev. 1.0)

  • Page 73: Watchdog Timer (Wdt)

    Use the following equation to calculate the WDT counter overflow cycle (NMI/reset generation cycle). 1,024 = —————— (Eq. 7.1) CLK_WDT Where Counter overflow cycle [second] CLK_WDT: WDT operating clock frequency [Hz] Example) = 4 seconds when CLK_WDT = 256 Hz Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 74: Clock Supply In Debug Mode

    If the clock source stops in SLEEP mode, WDT stops. To prevent generation of an unnecessary NMI or reset after clearing SLEEP mode, reset WDT before executing the slp instruction. WDT should also be stopped as required using the WDTCTL.WDTRUN[3:0] bits. Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 75: Control Registers

    1 (R/WP): NMI mode 0 (R/WP): Reset mode This bit is used to select whether an NMI signal or a reset signal is output when WDT has not been reset within the NMI/reset generation cycle. Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)
  • Page 76 Always 0x0 is read if a value other than 0xa is written. Since an NMI or reset may be generated immediately after running depending on the counter value, WDT should also be reset concurrently when running WDT. Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 77: Supply Voltage Detector (Svd)

    Clock generator CLKDIV[2:0] DBRUN SVDC[4:0] EXSVD Voltage VDSEL comparator SVDDT circuit Detection SVDSC[1:0] SVDIF result counter SVDIE SVDRE[3:0] Interrupt/reset To system reset circuit control circuit To interrupt controller Figure 8. 1.1 SVD Configuration Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 78: Input Pin And External Connection

    SLEEP mode and SVD stops with the register settings maintained at those before entering SLEEP mode. After the CPU returns to normal mode, CLK_SVD is supplied and the SVD operation resumes. Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 79: Clock Supply In Debug Mode

    SVDCTL.MODEN bit = 1, wait for at least SVD circuit response time before reading the SVDINTF.SVDDT bit (refer to “Supply Voltage Detector Characteristics, SVD circuit response time t ” in the “Electrical Char- acteristics” chapter). Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 80: Svd Operations

    SVDIF bit). An interrupt request is sent to the interrupt controller only when the SVDINTF.SVDIF bit is set while the interrupt is enabled by the SVDINTE.SVDIE bit. For more information on interrupt control, refer to the “Interrupt Controller” chapter. Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 81: Svd Reset

    0 (R/WP): No clock supplied in DEBUG mode Bit 7 Reserved Bits 6–4 ClKDiV[2:0] These bits select the division ratio of the SVD operating clock. Bits 3–2 Reserved Bits 1–0 ClKSRC[1:0] These bits select the clock source of SVD. Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 82: Svd Control Register

    SVDCTL.SVDC[4:0] bits Comparison voltage [V] 0x1f High 0x1e ↑ 0x0d ↓ 0x0c 0x0b–0x00 Use prohibited For more information, refer to “Supply Voltage Detector Characteristics, SVD detection voltage ” in the “Electrical Characteristics” chapter. Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 83: Svd Status And Interrupt Flag Register

    This bit indicates the low power supply voltage detection interrupt cause occurrence status. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 84: Svd Interrupt Enable Register

    Notes: • If the SVDCTL.SVDRE[3:0] bits are set to 0xa, no low power supply voltage detection in- terrupt will occur, as a reset is issued at the same timing as an interrupt. • To prevent generating unnecessary interrupts, clear the corresponding interrupt flag before enabling interrupts. Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 85: 16-Bit Timers (T16)

    If the port is shared with the EXCLm pin and other functions, the EXCLm input function must be assigned to the port before using the event counter function. The EXCLm signal can be input through the chattering filter. For more information, refer to the “I/O Ports” chapter. Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 86: Clock Settings

    (Set reload data (counter preset data)) 5. Set the following bits when using the interrupt: - Write 1 to the T16_nINTF.UFIF bit. (Clear interrupt flag) - Set the T16_nINTE.UFIE bit to 1. (Enable underflow interrupt) Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 87: Counter Underflow

    At the same time the counter stops, the T16_ nCTL.PRUN bit is cleared automatically. Select this mode to stop the counter after an interrupt has occurred once, such as for checking a specific lapse of time. Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 88: Counter Value Read

    Bits 7–4 ClKDiV[3:0] These bits select the division ratio of the T16 Ch.n operating clock (counter clock). Bits 3–2 Reserved Bits 1–0 ClKSRC[1:0] These bits select the clock source of T16 Ch.n. Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 89: T16 Ch.n Mode Register

    – PRESET MODEN Bits 15–9 Reserved Bit 8 PRun This bit starts/stops the timer. 1 (W): Start timer 0 (W): Stop timer 1 (R): Timer is running 0 (R): Timer is idle Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 90: T16 Ch.n Reload Data Register

    This bit indicates the T16 Ch.n underflow interrupt cause occurrence status. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 91: T16 Ch.n Interrupt Enable Register

    Bit 0 uFie This bit enables T16 Ch.n underflow interrupts. 1 (R/W): Enable interrupts 0 (R/W): Disable interrupts Note: To prevent generating unnecessary interrupts, clear the corresponding interrupt flag before enabling interrupts. Seiko epson Corporation S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 92: Uart (Uart)

    RZI modulator USOUTn TXD[7:0] INVIRTX IRMD Interrupt OUTMD controller TENDIE TENDIF FEIE FEIF Interrupt PEIE PEIF control circuit OEIE OEIF RB2FIE RB2FIF RB1FIE RB1FIF TBEIE TBEIF Figure 10. 1.1 UART Configuration Seiko epson Corporation S1C17F13 TeChniCal Manual 10-1 (Rev. 1.0)

  • Page 93: Input/Output Pins And External Connections

    When using the UART during SLEEP mode, the UART operating clock CLK_UARTn must be configured so that it will keep supplying by writing 0 to the CLGOSC.xxxxSLPC bit for the CLK_UARTn clock source. Seiko epson Corporation 10-2 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 94: Clock Supply In Debug Mode

    Parity function The parity function is configured using the UAnMOD.PREN and UAnMOD.PRMD bits. Table 10. 4.1 Parity Function Setting UAnMOD.PREN bit UAnMOD.PRMD bit Parity function Odd parity Even parity Non parity Seiko epson Corporation S1C17F13 TeChniCal Manual 10-3 (Rev. 1.0)

  • Page 95: Operations

    2. Write transmit data to the UAnTXD register. 3. Wait for a UART interrupt when using the interrupt. 4. Repeat Steps 1 to 3 (or 1 and 2) until the end of transmit data. Seiko epson Corporation 10-4 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 96: Data Reception

    2. Check to see if the UAnINTF.RB1FIF bit is set to 1 (receive buffer one byte full). 3. Read the received data from the UAnRXD register. 4. Repeat Steps 1 to 3 (or 2 and 3) until the end of data reception. Seiko epson Corporation S1C17F13 TeChniCal Manual 10-5 (Rev. 1.0)

  • Page 97: Irda Interface

    Set the UAnMOD.IRMD bit to 1 to use the IrDA interface. Data transfer control is identical to that for normal interface even if the IrDA interface function is enabled. Seiko epson Corporation 10-6 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 98: Receive Errors

    Note, however, that the set timing depends on the buffer status at that point. • When the receive data buffer is empty The interrupt flag will be set when the data that encountered an error is transferred to the re- ceive data buffer. Seiko epson Corporation S1C17F13 TeChniCal Manual 10-7 (Rev. 1.0)

  • Page 99: Parity Error

    Control Registers uaRT Ch.n Clock Control Register Register name Bit name Initial Reset Remarks UAnCLK 15–9 – 0x00 – – DBRUN 7–6 – – 5–4 CLKDIV[1:0] 3–2 – – 1–0 CLKSRC[1:0] Seiko epson Corporation 10-8 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 100: Uart Ch.n Mode Register

    1 (R/W): Enable output inverting function 0 (R/W): Disable output inverting function Bit 7 Reserved Bit 6 Puen This bit enables pull-up of the USINn pin. 1 (R/W): Enable pull-up 0 (R/W): Disable pull-up Seiko epson Corporation S1C17F13 TeChniCal Manual 10-9 (Rev. 1.0)

  • Page 101: Uart Ch.n Baud-Rate Register

    Note: The UAnBR register settings can be altered only when the UAnCTL.MODEN bit = 0. uaRT Ch.n Control Register Register name Bit name Initial Reset Remarks UAnCTL 15–8 – 0x00 – – 7–2 – 0x00 – SFTRST MODEN Bits 15–2 Reserved Seiko epson Corporation 10-10 S1C17F13 TeChniCal Manual (Rev. 1.0)
  • Page 102 PEIF H0/S0 OEIF H0/S0 Cleared by writing 1. RB2FIF H0/S0 Cleared by reading the UAnRXD reg- ister. RB1FIF H0/S0 TBEIF H0/S0 Cleared by writing to the UAnTXD register. Bits 15–10 Reserved Seiko epson Corporation S1C17F13 TeChniCal Manual 10-11 (Rev. 1.0)
  • Page 103 Bit 5 Feie Bit 4 Peie Bit 3 Oeie Bit 2 RB2Fie Bit 1 RB1Fie Bit 0 TBeie These bits enable UART interrupts. 1 (R/W): Enable interrupts 0 (R/W): Disable interrupts Seiko epson Corporation 10-12 S1C17F13 TeChniCal Manual (Rev. 1.0)
  • Page 104 UAnINTE.PEIE bit: Parity error interrupt UAnINTE.OEIE bit: Overrun error interrupt UAnINTE.RB2FIE bit: Receive buffer two bytes full interrupt UAnINTE.RB1FIE bit: Receive buffer one byte full interrupt UAnINTE.TBEIE bit: Transmit buffer empty interrupt Seiko epson Corporation S1C17F13 TeChniCal Manual 10-13 (Rev. 1.0)
  • Page 105 RXD[7:0] LSBFST CPHA SPICLKn CPOL Pull-up/down control PUEN circuit (Used only in slave mode) #SPISSn Interrupt controller Interrupt TENDIE TENDIF control circuit RBFIE RBFIF TBEIE TBEIF Figure 11. 1.1 SPI Configuration Seiko epson Corporation S1C17F13 TeChniCal Manual 11-1 (Rev. 1.0)

  • Page 106: Input/Output Pins And External Connections

    #SPISS0 SPICLKn #SPISS1 #SPISS #SPISS2 External SPI master device External SPI slave devices SPICLK SPICLK #SPISS SPICLK Figure 11. 2.2.2 Connections between SPI in Slave Mode and External SPI Master Device Seiko epson Corporation 11-2 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 107: Pin Functions In Master Mode And Slave Mode

    16-bit timer channel and converts it to the SPICLKn. The 16-bit timer must be run with an appro- priate reload data set. The SPICLKn frequency (baud rate) and the 16-bit timer reload data are calculated by the equations shown below. Seiko epson Corporation S1C17F13 TeChniCal Manual 11-3 (Rev. 1.0)

  • Page 108: Spi Clock (Spiclkn) Phase And Polarity

    SPICLKn SPICLKn SDIn SDOn (Master mode) SDOn (Slave mode) SDOn (Slave mode) Writing data to the SPInTXD register Figure 11. 3.3.1 SPI Clock Phase and Polarity (SPI nMOD.LSBFST bit = 0) Seiko epson Corporation 11-4 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 109: Data Format

    2. Check to see if the SPInINTF.TBEIF bit is set to 1 (transmit buffer empty). 3. Write transmit data to the SPInTXD register. 4. Wait for an SPI interrupt when using the interrupt. Seiko epson Corporation S1C17F13 TeChniCal Manual 11-5 (Rev. 1.0)
  • Page 110 SPInTXD register Transmit data remained? Wait for an interrupt request (SPInINTF.TBEIF = 1) Negate the slave select signal output from a general-purpose port Figure 11. 5.2.2 Data Transmission Flowchart in Master Mode Seiko epson Corporation 11-6 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 111: Data Reception In Master Mode

    SPInRXD → Data (R) Software operations SPInRXD → Data (R) Data (W) → SPInTXD SPInRXD → Data (R) 1 (W) → SPInINTF.TENDIF Figure 11. 5.3.1 Example of Data Receiving Operations in Master Mode Seiko epson Corporation S1C17F13 TeChniCal Manual 11-7 (Rev. 1.0)

  • Page 112: Terminating Data Transfer In Master Mode

    1. Wait for a receive buffer full interrupt (SPInINTF.RBFIF bit = 1). 2. Read the received data from the SPInRXD register. 3. Repeat Steps 1 and 2 until the end of data reception. Seiko epson Corporation 11-8 S1C17F13 TeChniCal Manual (Rev. 1.0)
  • Page 113 SPInRXD register Write transmit data to Receive data remained? the SPInTXD register Transmit data remained? Wait for an interrupt request (SPInINTF.TBEIF = 1) Figure 11. 5.5.2 Data Transfer Flowcharts in Slave Mode Seiko epson Corporation S1C17F13 TeChniCal Manual 11-9 (Rev. 1.0)

  • Page 114: Terminating Data Transfer In Slave Mode

    Slave mode #SPISSn SPInINTF.BSY SPInMOD register CPOL bit CPHA bit SPICLKn SDOn SPICLKn SDOn SPInINTF.TENDIF Writing data to the SPInTXD register Figure 11. 6.1 SPI nINTF.BSY and SPInINTF.TENDIF Bit Set Timings Seiko epson Corporation 11-10 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 115: Spi Ch.n Mode Register

    Note: The SPInMOD register settings can be altered only when the SPInCTL.MODEN bit = 0. SPi Ch.n Control Register Register name Bit name Initial Reset Remarks SPInCTL 15–8 – 0x00 – – 7–2 – 0x00 – SFTRST MODEN Bits 15–2 Reserved Seiko epson Corporation S1C17F13 TeChniCal Manual 11-11 (Rev. 1.0)

  • Page 116: Spi Ch.n Transmit Data Register

    15–8 – 0x00 – – 7–4 – – TENDIF H0/S0 Cleared by writing 1. RBFIF H0/S0 Cleared by reading the SPInRXD register. TBEIF H0/S0 Cleared by writing to the SPInTXD register. Seiko epson Corporation 11-12 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 117: Spi Ch.n Interrupt Enable Register

    1 (R/W): Enable interrupts 0 (R/W): Disable interrupts The following shows the correspondence between the bit and interrupt: SPInINTE.TENDIE bit: End-of-transmission interrupt SPInINTE.RBFIE bit: Receive buffer full interrupt SPInINTE.TBEIE bit: Transmit buffer empty interrupt Seiko epson Corporation S1C17F13 TeChniCal Manual 11-13 (Rev. 1.0)

  • Page 118: C (I2C)

    OADR[9:0] Slave mode GCEN controller SDALOW SCLLOW TXNACK TXSTART Master mode TXSTOP controller SCLn CLKSRC[1:0] CLKDIV[1:0] Clock generator DBRUN Baud rate SCLO MODEN BRT[6:0] generator CLK_I2Cn Figure 12. 1.1 I2C Configuration Seiko epson Corporation S1C17F13 TeChniCal Manual 12-1 (Rev. 1.0)

  • Page 119: Input/Output Pins And External Connections

    • The internal pull-up resistors for the I/O ports cannot be used for pulling up SDA and SCL. • When the I2C is set into master mode, no other master device can be connected to the I bus. Seiko epson Corporation 12-2 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 120: Clock Settings

    12.3.3.1). Note: The I C bus transfer rate is limited to 100 kbit/s in standard mode or 400 kbit/s in fast mode. Do not set a transfer rate exceeding the limit. Seiko epson Corporation S1C17F13 TeChniCal Manual 12-3 (Rev. 1.0)

  • Page 121: Operations

    - Set the I2CnCTL.MST bit to 0. (Set slave mode) - Set the I2CnCTL.SFTRST bit to 1. (Execute software reset) - Set the I2CnCTL.MODEN bit to 1. (Enable I2C Ch.n operations) Seiko epson Corporation 12-4 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 122: Data Transmission In Master Mode

    I2CnINTF.NACKIF bit = 1 (NACK received), the I2C Ch.n generates a repeated START condition. When the repeated START condition has been generated, the I2CnINTF.STARTIF and I2CnINTF.TBEIF bits are both set to 1 same as when a START condition has been generated. Seiko epson Corporation S1C17F13 TeChniCal Manual 12-5 (Rev. 1.0)
  • Page 123 Last data sent? Retry? Write 1 to the I2CnCTL.TXSTOP bit Write data to the I2CnTXD register Wait for an interrupt request (I2CnINTF.STOPIF = 1) Figure 12. 4.2.2 Master Mode Data Transmission Flowchart Seiko epson Corporation 12-6 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 124: Data Reception In Master Mode

    RXD register. This reading triggers the I2C Ch.n to start subsequent data reception. Generating a STOP or repeated START condition It is the same as the data transmission in master mode. Seiko epson Corporation S1C17F13 TeChniCal Manual 12-7 (Rev. 1.0)
  • Page 125 Read receive data from the I2CnRXD register Write 1 to the I2CnCTL.TXSTOP bit Write 1 to the I2CnCTL.TXSTOP bit Wait for an interrupt request (I2CnINTF.STOPIF = 1) Figure 12. 4.3.2 Master Mode Data Reception Flowchart Seiko epson Corporation 12-8 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 126: 10-Bit Addressing In Master Mode

    Clear the I2CnINTF.STARTIF bit by writing 1 after the interrupt has occurred. 9. Write the first address to the I2CnTXD.TXD[7:1] bits and 1 that represents READ as the data transfer direc- tion to the I2CnTXD.TXD0 bit. 10. Perform data reception. Seiko epson Corporation S1C17F13 TeChniCal Manual 12-9 (Rev. 1.0)

  • Page 127: Data Transmission In Slave Mode

    Go to Step 6 when a STOP condition interrupt has occurred. ii. Go to Step 2 when a START condition interrupt has occurred. 6. Clear the I2CnINTF.STOPIF bit and then terminate data sending operations. Seiko epson Corporation 12-10 S1C17F13 TeChniCal Manual (Rev. 1.0)
  • Page 128 A: ACK, A: NACK, Saddr/R: Slave address + R(1), Saddr/W: Slave address + W(0), STARTIF = 1 Data n: 8-bit data Figure 12. 4.5.1 Example of Data Sending Operations in Slave Mode Seiko epson Corporation S1C17F13 TeChniCal Manual 12-11 (Rev. 1.0)

  • Page 129: Data Reception In Slave Mode

    After eight-bit data has been received, the I2C Ch.n sends an ACK and pulls down SCL to low. The received data in the shift register is transferred to the receive data buffer and the I2CnINTF.RBFIF and I2CnINTF.BYTEENDIF bits are both set to 1. Seiko epson Corporation 12-12 S1C17F13 TeChniCal Manual (Rev. 1.0)
  • Page 130 (I2CnINTF.RBFIF = 1) Last data received next? Write 1 to the I2CnCTL.TXNACK bit Read receive data from the I2CnRXD register Last data received? Figure 12. 4.6.2 Slave Mode Data Reception Flowchart Seiko epson Corporation S1C17F13 TeChniCal Manual 12-13 (Rev. 1.0)

  • Page 131: Slave Operations In 10-Bit Address Mode

    If SDA does not change from low when the I2C Ch.n outputs the ninth clock, it is regarded as an automatic bus clearing failure. In this case, the I2C Ch.n clears the I2CnCTL.TXSTART bit to 0 and sets both the I2CnINTF.ERRIF and I2CnINTF.STARTIF bits to 1. Seiko epson Corporation 12-14 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 132: Error Detection

    4 <Master mode only> When 1 is written to the I2CnCTL.TX- I2CnINTF.ERRIF = 1 START bit while the I2CnINTF.BSY bit = 0 (Refer to “Automatic Automatic bus clearing I2CnCTL.TXSTART = 0 Bus Clearing Operation.”) failure I2CnINTF.STARTIF = 1 Seiko epson Corporation S1C17F13 TeChniCal Manual 12-15 (Rev. 1.0)

  • Page 133: Interrupts

    Master mode BRT + 3 CLK_I2Cn TXSTART = 1 TXSTART = 0 STARTIF = 1 Slave mode Address matching the I2CnOADR register BSY = 1 TR = 0/1 STARTIF = 1 Seiko epson Corporation 12-16 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 134: Control Registers

    (Note) The oscillation circuits/external input that are not supported in this IC cannot be selected as the clock source. Note: The I2CnCLK register settings can be altered only when the I2CnCTL.MODEN bit = 0. Seiko epson Corporation S1C17F13 TeChniCal Manual 12-17 (Rev. 1.0)

  • Page 135: I2C Ch.n Mode Register

    The I2CnOADR.OADR[9:0] bits are effective in 10-bit address mode (I2CnMOD.OADR10 bit = 1), or the I2CnOADR.OADR[6:0] bits are effective in 7-bit address mode (I2CnMOD.OADR10 bit = 0). Note: The I2CnOADR register settings can be altered only when the I2CnCTL.MODEN bit = 0. Seiko epson Corporation 12-18 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 136: I2C Ch.n Control Register

    Bit 0 MODen This bit enables the I2C operations. 1 (R/W): Enable I2C operations (The operating clock is supplied.) 0 (R/W): Disable I2C operations (The operating clock is stopped.) Seiko epson Corporation S1C17F13 TeChniCal Manual 12-19 (Rev. 1.0)

  • Page 137: I2C Ch.n Transmit Data Register

    Cleared by writing to the I2CnTXD register. Bits 15–13 Reserved Bit 12 SDalOW This bit indicates that SDA is set to low level. 1 (R): SDA = Low level 0 (R): SDA = High level Seiko epson Corporation 12-20 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 138: I2C Ch.n Interrupt Enable Register

    Transmit buffer empty interrupt i2C Ch.n interrupt enable Register Register name Bit name Initial Reset Remarks I2CnINTE 15–8 – 0x00 – – BYTEENDIE GCIE NACKIE STOPIE STARTIE ERRIE RBFIE TBEIE Bits 15–8 Reserved Seiko epson Corporation S1C17F13 TeChniCal Manual 12-21 (Rev. 1.0)
  • Page 139 I2CnINTE.NACKIE bit: NACK reception interrupt I2CnINTE.STOPIE bit: STOP condition interrupt I2CnINTE.STARTIE bit: START condition interrupt I2CnINTE.ERRIE bit: Error detection interrupt I2CnINTE.RBFIE bit: Receive buffer full interrupt I2CnINTE.TBEIE bit: Transmit buffer empty interrupt Seiko epson Corporation 12-22 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 140: Clock Timer (Ct)

    CTCTL.MODEN bit. When 0 is written to the CTCTL.MODEN bit, the timer stops after counting an additional “+1.” 1 is retained for the CTCTL.MODEN bit reading until the timer actually stops. Figure 13.3.1 shows the run/stop control timing chart. Seiko epson Corporation S1C17F13 TeChniCal Manual 13-1 (Rev. 1.0)

  • Page 141: Interrupts

    For more information on interrupt control, refer to the “Interrupt Controller” chapter. Seiko epson Corporation 13-2 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 142: Control Registers

    Note: The correct counter value may not be read out (reading is unstable) if the register is read while counting is underway. Read the counter register twice in succession and treat the value as valid if the values read are identical. Seiko epson Corporation S1C17F13 TeChniCal Manual 13-3 (Rev. 1.0)

  • Page 143: Ct Interrupt Flag Register

    0 (R/W): Disable interrupts The following shows the correspondence between the bit and interrupt: CTINTE.CT32HZIE bit: 32 Hz interrupt CTINTE.CT8HZIE bit: 8 Hz interrupt CTINTE.CT2HZIE bit: 2 Hz interrupt CTINTE.CT1HZIE bit: 1 Hz interrupt Seiko epson Corporation 13-4 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 144: Real-Time Clock (Rtc)

    The counter is cleared to 0 when it reaches 60 seconds and outputs a carry over of 1 to the minute counter. The counter data can be read/written using the RTCMIN.RTCSEC[6:0] bits. Seiko epson Corporation S1C17F13 TeChniCal Manual 14-1 (Rev. 1.0)
  • Page 145 0x06 19 o'clock (7pm) 0x13 0x19 0x07 20 o'clock (8pm) 0x14 0x20 0x08 21 o'clock (9pm) 0x15 0x21 0x09 22 o'clock (10pm) 0x16 0x22 0x10 23 o'clock (11pm) 0x17 0x23 0x11 Seiko epson Corporation 14-2 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 146: Operations

    RTC idle time = [#RESET = low period] + [Boot clock oscillation stabilization time] + [Time until OSC1 is started] + [OSC1 oscillation stabilization time] + [Time until RTC is restarted] Seiko epson Corporation S1C17F13 TeChniCal Manual 14-3 (Rev. 1.0)

  • Page 147: Time Read

    For more information on interrupt control, refer to the “Interrupt Controller” chapter. Seiko epson Corporation 14-4 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 148: Control Registers

    When the RTC stops counting by writing 0 to this bit, the counter retains the value when it was stopped. Writing 1 to this bit again resumes counting from the value retained. Writing 1 to the RTCCTL.RTCRUN bit resets the OSC1A divider in the clock generator. Seiko epson Corporation S1C17F13 TeChniCal Manual 14-5 (Rev. 1.0)

  • Page 149: Rtc Interrupt Enable Register

    RTC interrupt Flag Register Register name Bit name Initial Reset Remarks RTCINTF 15–10 – 0x00 – – 1DIF Cleared by writing 1. HDIF 1HIF 10MIF 1MIF 10SIF 1HZIF 4HZIF 8HZIF 32HZIF Bits 15–10 Reserved Seiko epson Corporation 14-6 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 150: Rtc Minute/Second Register

    For the configuration of the second counter, see “RTC Counters.” For the counter read and write procedures, see “Operations.” RTC hour Register Register name Bit name Initial Reset Remarks RTCHUR 15–8 – 0x00 – – AMPM – – – 5–0 RTCHUR[5:0] – Seiko epson Corporation S1C17F13 TeChniCal Manual 14-7 (Rev. 1.0)
  • Page 151 These bits are used to read and write data from/to the hour counter. For the configuration of the hour counter, see “RTC Counters.” For the counter read and write procedures, see “Operations.” Seiko epson Corporation 14-8 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 152: Theoretical Regulation (Tr)

    2. Generate interrupts in the theoretical regulation execution cycles using a timer to perform theoretical regulation periodically. 3. Write 1 to the TRCTL.REGTRIG bit (using the interrupt handler in Step 2). (Execute theoretical regulation) Seiko epson Corporation S1C17F13 TeChniCal Manual 15-1 (Rev. 1.0)
  • Page 153 Note: Use an interrupt from a timer that runs with the regulated clock (F256) to execute theoretical regulation. An interrupt from the timer that runs all the time should be used to reduce current consumption. Seiko epson Corporation 15-2 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 154: Regulated Clock External Monitor

    TRCTL.REGTRIG bit. Writing 1 to the TRCTL.REGTRIG bit in this period is ineffective, so to write 1 to the TRCTL.REGTRIG bit successively, an interval at least 16.6 ms is neces- sary between writings. Seiko epson Corporation S1C17F13 TeChniCal Manual 15-3 (Rev. 1.0)
  • Page 155 15 THEORETICAL REGULATION (TR) Bit 6 Reserved Bits 5–0 TRiM[5:0] These bits specify the correction value (-31/32,768 to +32/32,768 seconds) for theoretical regulation. Seiko epson Corporation 15-4 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 156: 16-Bit Pwm Timers (T16A3)

    • Capture signal input: Ch.0 Two inputs with CAPA0 and CAPB0 pins Ch.1 Two inputs with CAPA1 and CAPB1 pins • Half-clock mode: Ch.0 Available Ch.1 Available • Multi-comparator/capture mode: Ch.0 Available Ch.1 Available Seiko epson Corporation S1C17F13 TeChniCal Manual 16-1 (Rev. 1.0)

  • Page 157: Input/Output Pins

    When an external clock is used, select the EXCLm pin function (refer to the “I/O Ports” chapter). 2. Set the following T16AnCLK register bits: - T16AnCLK.CLKSRC[1:0] bits (Clock source selection) - T16AnCLK.CLKDIV[3:0] bits (Clock division ratio selection = Clock frequency setting) Seiko epson Corporation 16-2 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 158: Clock Supply In Sleep Mode

    5. Set the following bits when using the interrupt: - Write 1 to the interrupt flags in the T16AnINTF register. (Clear interrupt flags) - Set the interrupt enable bits in the T16AnINTE register to 1. (Enable interrupts) Seiko epson Corporation S1C17F13 TeChniCal Manual 16-3 (Rev. 1.0)

  • Page 159: Counter Block Operations

    B signal is generated. Select this mode to stop the counter after an interrupt has occurred once, such as for checking a specific lapse of time. Seiko epson Corporation 16-4 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 160: Comparator/Capture Block Operations

    Counter Time 0x0000 CMPBIF = 1 CMPBIF = 1 (Note that the T16AnINTF.CMPBIF/CMPAIF bit clearing operations via software are omitted from the figure.) Figure 16. 4.3.1 Operations in Comparator Mode Seiko epson Corporation S1C17F13 TeChniCal Manual 16-5 (Rev. 1.0)
  • Page 161 CMPAIF = 1 CMPAIF = 1 CMPAIF = 1 (Note that the T16AnINTF.CMPBIF/CMPAIF bit clearing operations via software are omitted from the figure.) Figure 16. 4.3.2 Compare Buffer Operations (Counter = Repeat Mode) Seiko epson Corporation 16-6 S1C17F13 TeChniCal Manual (Rev. 1.0)
  • Page 162 CCABCNT[1:0] bits. This enables a counter block channel to connect to two or more comparator/capture block channels. Note, however, that all channels must use the count clock configured in the counter block Ch.0, and a different count clock cannot be used in each channel. Seiko epson Corporation S1C17F13 TeChniCal Manual 16-7 (Rev. 1.0)
  • Page 163 Counter block Comparator/capture block Ch.1 Ch.1 CLK_T16A1 Counter block Comparator/capture block Ch.2 Ch.2 CLK_T16A2 Counter block Comparator/capture block Ch.3 Ch.3 CLK_T16A3 Figure 16. 4.3.5 Timer Configuration in Multi-Comparator/Capture Mode (e.g., 4 channels) Seiko epson Corporation 16-8 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 164: Tout Output Control

    1 2 3 4 5 0 1 2 3 4 5 0 1 Compare A signal Compare B signal TOUT(A) output T16AnCCCTL register TOUTAMD[1:0] TOUTAINV (When T16AnCCA.CCA[15:0] = 3, T16AnCCB.CCB[15:0] = 5) Figure 16. 4.4.2 TOUT Output Waveform Seiko epson Corporation S1C17F13 TeChniCal Manual 16-9 (Rev. 1.0)
  • Page 165 Example: T16AnCTL.HCM = 1, T16AnCCA.CCA[15:0] = 1, and T16AnCCB.CCB[15:0] = 5 (When T16AnCCCTL.TOUTAMD[1:0] = TOUTBMD[1:0] = 0x1 and T16AnCCCTL.TOUTAINV = TOUTBINV = 0) Count clock T16AnTC.T16ATC[15:0] Dual-edge counter – – TOUTAn/TOUTBn Figure 16. 4.4.4 PWM Waveform Output Timings in Half-Clock Mode Seiko epson Corporation 16-10 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 166: Interrupt

    For detailed information, refer to “Comparator/Capture Block Operations, Multi-comparator/capture mode and the counter channel used.” Bit 2 Reserved (T16a3 Ch.1–n) Bits 1–0 ClKSRC[1:0] These bits select the clock source of T16A3 Ch.n. Seiko epson Corporation S1C17F13 TeChniCal Manual 16-11 (Rev. 1.0)

  • Page 167: T16A3 Counter Ch.n Control Register

    This bit sets T16A3 to half-clock mode. 1 (R/W): Enable (half-clock mode) 0 (R/W): Disable (normal clock mode) For detailed information, refer to “TOUT Output Control, PWM waveform output and normal clock/ half-clock mode.” Seiko epson Corporation 16-12 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 168: T16A3 Counter Ch.n Data Register

    T16a3 Counter Ch.n Data Register Register name Bit name Initial Reset Remarks T16AnTC 15–0 T16ATC[15:0] 0x0000 – Bits 15–0 T16aTC[15:0] The current counter value can be read out through these bits. Seiko epson Corporation S1C17F13 TeChniCal Manual 16-13 (Rev. 1.0)

  • Page 169: T16A3 Comparator/Capture Ch.n Control Register

    0 (R/W): Comparator mode (T16AnCCB register = compare B register) Bits 7–6 CaPaTRG[1:0] These bits select the trigger edge(s) of the external signal (CAPAn) at which the counter value is cap- tured in the T16AnCCA register. Seiko epson Corporation 16-14 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 170: T16A3 Comparator/Capture Ch.n A Data Register

    Bits 15–0 CCB[15:0] In comparator mode (T16AnCCCTL.CCBMD bit = 0), this register is configured as the compare B register and used to set compare B data that is compared with the counter value. Seiko epson Corporation S1C17F13 TeChniCal Manual 16-15 (Rev. 1.0)

  • Page 171: T16A3 Ch.n Interrupt Flag Register

    Compare A interrupt T16a3 Ch.n interrupt enable Register Register name Bit name Initial Reset Remarks T16AnINTE 15–8 – 0x00 – – 7–6 – – CAPBOWIE CAPAOWIE CAPBIE CAPAIE CMPBIE CMPAIE Bits 15–6 Reserved Seiko epson Corporation 16-16 S1C17F13 TeChniCal Manual (Rev. 1.0)
  • Page 172 Capture B interrupt T16AnINTE.CAPAIE bit: Capture A interrupt T16AnINTE.CMPBIE bit: Compare B interrupt T16AnINTE.CMPAIE bit: Compare A interrupt Note: To prevent generating unnecessary interrupts, clear the corresponding interrupt flag before enabling interrupts. Seiko epson Corporation S1C17F13 TeChniCal Manual 16-17 (Rev. 1.0)

  • Page 173: Parallel Interface (Pio) Characteristics

    If the port is shared with the PIO pin and other functions, the PIO input/output function must be assigned to the port before activating PIO. For more information, refer to the “I/O Ports” chapter. Seiko epson Corporation S1C17F13 TeChniCal Manual 17-1 (Rev. 1.0)

  • Page 174: External Connections

    PIO should be initialized with the procedure shown below. 1. Assign the PIO input/output function to the ports. (Refer to the “I/O Ports” chapter.) 2. Set the PIOCLK.CLKSRC[1:0] and PIOCLK.CLKDIV[1:0] bits. (Configure operating clock) Seiko epson Corporation 17-2 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 175: Operations In Sram Mode

    2. Write 1 to the PIOCTL.RACC bit. (Data read trigger) 3. Wait until the PIOSTAT.RBUSY bit goes to 0. 4. Read the input data from the PIORDDAT.PRDATA[7:0] bits. 5. Repeat Steps 1 to 4 until the end of data input. Seiko epson Corporation S1C17F13 TeChniCal Manual 17-3 (Rev. 1.0)

  • Page 176: Operations In Gpio Mode

    The PIOD[7:0] pin status is sampled in the CLK_PIO clock cycles and loaded to the PIORDDAT.PRDATA[7:0] bits. Therefore, maximum one CLK_PIO cycle of delay occurs until the input transition is reflected to the PI- ORDDAT.PRDATA[7:0] bits. Seiko epson Corporation 17-4 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 177: Control Registers

    This bit enables pull-up of the PIO pins. 1 (R/W): Enable pull-up 0 (R/W): Disable pull-up Bit 0 GPiOMD This bit sets PIO to GPIO mode. 1 (R/W): GPIO mode 0 (R/W): SRAM mode Seiko epson Corporation S1C17F13 TeChniCal Manual 17-5 (Rev. 1.0)

  • Page 178: Pio Control Register

    OSTAT.WBUSY bit = 1) and read cycle (when the PIOSTAT.RBUSY bit = 1). PiO Read Data Register Register name Bit name Initial Reset Remarks PIORDDAT 15–8 – 0x00 – – 7–0 PRDATA[7:0] 0x00 Bits 15–8 Reserved Seiko epson Corporation 17-6 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 179: Pio Status Register

    1 (R): Write cycle is being executed. 0 (R): Idle Bit 0 RBuSY This bit indicates the read cycle operating status. 1 (R): Read cycle is being executed. 0 (R): Idle Seiko epson Corporation S1C17F13 TeChniCal Manual 17-7 (Rev. 1.0)

  • Page 180: Epd Timing Controller (Epd Tcon)

    For the data format in the display RAM, various settings, and operations, refer to the descriptions of the EPD Tcon API library (EPD Timing Controller S1C17F13 Manual (separately attached sheet)). Note: EPD Tcon occupies SPI Ch.1 or the parallel interface while it is running. This peripheral circuit cannot be accessed from the S1C17.

  • Page 181: Control Registers

    EPDINTE 15–8 – 0x00 – – 7–1 – 0x00 – ENDIE Bits 15–1 Reserved Bit 0 enDie This bit enables EPD Tcon interrupts. 1 (R/W): Enable interrupts 0 (R/W): Disable interrupts Seiko epson Corporation 18-2 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 182: R/F Converter (Rfc)

    DBRUN TC[23:0] MODEN Counter RFCLKOn control circuit Measurement counter MC[23:0] CONEN SSENB RFINn EVTEN CR oscillation SSENA Oscillation REFn SMODE[1:0] control circuit SREF circuit SENAn SENBn Figure 19. 1.1 RFC Configuration Seiko epson Corporation S1C17F13 TeChniCal Manual 19-1 (Rev. 1.0)

  • Page 183: Input/Output Pins And External Connections

    2.2.1 Connection Example in Resistive Sensor DC Oscillation Mode SENBn SEN1 SENAn REFn RFINn : Reference resistor : Resistive sensor (AC bias) SEN1 S1C17 RFC : Oscillation capacitor Figure 19. 2.2.2 Connection Example in Resistive Sensor AC Oscillation Mode Seiko epson Corporation 19-2 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 184: Clock Settings

    (Clear interrupt flags) - Set the interrupt enable bits in the RFCnINTE register to 1. (Enable interrupts) 3. Assign the RFC input/output function to the ports. (Refer to the “I/O Ports” chapter.) Seiko epson Corporation S1C17F13 TeChniCal Manual 19-3 (Rev. 1.0)

  • Page 185: Operating Modes

    To obtain the difference between the reference oscillation and sensor oscillation clock count values from the measurement counter simply, appropriate initial values must be set to the measurement counter before starting reference oscillation. Seiko epson Corporation 19-4 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 186: Converting Operations And Control Procedure

    The measurement counter overflow sets the RFCnINTF.EREFIF bit to 1 indicating that the reference oscil- lation has been terminated normally. If the RFCnINTE.EREFIE bit = 1, a reference oscillation completion interrupt request occurs at this point. Seiko epson Corporation S1C17F13 TeChniCal Manual 19-5 (Rev. 1.0)
  • Page 187 Performing reference oscillation and sensor oscillation with the same resistor and capacitor results n ≈ m. The difference between n and m is a conversion error. Table 19.4.4.1 lists the error factors. (n: measurement counter initial value, m: measurement counter value at the end of sensor oscillation) Seiko epson Corporation 19-6 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 188: Cr Oscillation Frequency Monitoring Function

    For more information on interrupt control, refer to the “Interrupt Controller” chapter. Seiko epson Corporation S1C17F13 TeChniCal Manual 19-7 (Rev. 1.0)

  • Page 189: Control Registers

    This bit sets the RFCLKOn pin to output the divided-by-two oscillation clock. 1 (R/W): Divided-by-two clock output 0 (R/W): Oscillation clock output For more information, refer to “CR Oscillation Frequency Monitoring Function.” Seiko epson Corporation 19-8 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 190: Rfc Ch.n Oscillation Trigger Register

    This bit controls CR oscillation for sensor A. This bit also indicates the CR oscillation status. 1 (W): Start oscillation 0 (W): Stop oscillation 1 (R): Being oscillated 0 (R): Stopped Seiko epson Corporation S1C17F13 TeChniCal Manual 19-9 (Rev. 1.0)

  • Page 191: Rfc Ch.n Measurement Counter Low And High Registers

    Note: The time base counter must be set from the low-order value (RFCnTCL.TC[15:0] bits) first when data is set using a 16-bit access instruction. The counter may not be set to the correct value if the high-order value (RFCnTCH.TC[23:16] bits) is written first. Seiko epson Corporation 19-10 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 192: Rfc Ch.n Interrupt Flag Register

    RFCnINTE.OVTCIE bit: Time base counter overflow error interrupt RFCnINTE.OVMCIE bit: Measurement counter overflow error interrupt RFCnINTE.ESENBIE bit: Sensor B oscillation completion interrupt RFCnINTE.ESENAIE bit: Sensor A oscillation completion interrupt RFCnINTE.EREFIE bit: Reference oscillation completion interrupt Seiko epson Corporation S1C17F13 TeChniCal Manual 19-11 (Rev. 1.0)

  • Page 193: Temperature Detection Circuit (Tem)

    CLKSRC[1:0] TEMST Clock CLKDIV[1:0] Comparator generator DBRUN TEMP[7:0] Comparison Comparison time setting voltage CLK_TEM circuit setting circuit CVTM[7:0] TEMTRG TEMIE Interrupt Interrupt controller control circuit TEMIF Figure 20. 1.1 TEM Configuration Seiko epson Corporation S1C17F13 TeChniCal Manual 20-1 (Rev. 1.0)
  • Page 194 Be sure to set a 150 µs or more comparison time including clock frequency dispersion. CVTM + 1 Comparison time = —————— ≥ 150 [µs] (Eq. 20.1) CLK_TEM Where CVTM: TEMTMG.CVTM[7:0] bit setting value (0 to 255) CLK_TEM: CLK_TEM frequency [Hz] Seiko epson Corporation 20-2 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 195: Temperature Detection

    Figure 20. 3.3.1 Temperature Conversion Operation Correspondence between detection results and temperature The table below lists the temperature (within the detection range) corresponding to the 8-bit value read from the TEMRSLT.TEMP[7:0] bits. Seiko epson Corporation S1C17F13 TeChniCal Manual 20-3 (Rev. 1.0)
  • Page 196 Note: The detection results are the temperature inside the device detected by the sensor embedded in the device. Seiko epson Corporation 20-4 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 197: Interrupt

    Note: The TEMCLK register settings can be altered only when the TEMCTL.MODEN bit = 0. TeM Timing Register Register name Bit name Initial Reset Remarks TEMTMG 15–8 – 0x00 – – 7–0 CVTM[7:0] 0x00 Bits 15–8 Reserved Seiko epson Corporation S1C17F13 TeChniCal Manual 20-5 (Rev. 1.0)

  • Page 198: Tem Control Register

    Bit 0 TeMiF This bit indicates the TEM interrupt cause occurrence status. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective Seiko epson Corporation 20-6 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 199: Tem Interrupt Enable Register

    Remarks TEMINTE 15–8 – 0x00 – – 7–1 – 0x00 – TEMIE Bits 15–1 Reserved Bit 0 TeMie This bit enables TEM interrupts. 1 (R/W): Enable interrupts 0 (R/W): Disable interrupts Seiko epson Corporation S1C17F13 TeChniCal Manual 20-7 (Rev. 1.0)

  • Page 200: Multiplier/Divider (Copro)

    %rs[6:0] is written to the mode setting register. (%rd: not used) ld.cw %rd,%rs imm7[6:0] is written to the mode setting register. (%rd: not used) ld.cw %rd,imm7 Output mode setting value Operation mode setting value Figure 21. 2.1 Mode Setting Register Seiko epson Corporation S1C17F13 TeChniCal Manual 21-1 (Rev. 1.0)

  • Page 201: Multiplication

    COPRO Argument 2 Argument 1 16 bits 32 bits Operation S1C17 Core result Operation result register Selector Coprocessor output (16 bits) Flag output Figure 21. 3.1 Data Path in Multiplication Mode Seiko epson Corporation 21-2 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 202: Division

    0x018 res[31:0] ← %rd ÷ %rs ld.ca %rd,%rs or 0x19 %rd ← res[31:16] (residue) (ext res[31:0] ← %rd ÷ imm7/16 imm9) %rd ← res[31:16] (residue) ld.ca %rd,imm7 res: operation result register Seiko epson Corporation S1C17F13 TeChniCal Manual 21-3 (Rev. 1.0)
  • Page 203 6. Read another one-half result (16 high-order bits = A[31:16]). COPRO Argument 2 Argument 1 16 bits 32 bits S1C17 Core Operation result register Selector Coprocessor output (16 bits) Flag output Figure 21. 5.1 Data Path in Initialize Mode Seiko epson Corporation 21-4 S1C17F13 TeChniCal Manual (Rev. 1.0)
  • Page 204 An overflow occurs in a MAC operation and the overflow (V) flag is set to 1 when the signs of the multiplica- tion result, operation result register value, and multiplication & accumulation result match the following condi- tions: Seiko epson Corporation S1C17F13 TeChniCal Manual 21-5 (Rev. 1.0)

  • Page 205: Reading Operation Results

    (CVZN) ← 0b0000 This operation mode does not ld.ca %rd,%rs affect the operation result reg- ld.ca %rd,imm7 %rd ← res[15:0] ister. 0x13 %rd ← res[31:16] ld.ca %rd,%rs ld.ca %rd,imm7 %rd ← res[31:16] res: operation result register Seiko epson Corporation 21-6 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 206: Electrical Characteristics

    Capacitor between V and V – 0.22 – µF DSIO pull-up resistor – – *1 The C , and C pins can be left open when Flash programming is not performed. Seiko epson Corporation S1C17F13 TeChniCal Manual 22-1 (Rev. 1.0)

  • Page 207: Current Consumption

    *2 The current consumption values were measured when a test program consisting of 60.5 % ALU instructions, 17 % branch in- structions, 12 % RAM read instructions, and 10.5 % RAM write instructions was executed continuously in the RAM. Seiko epson Corporation 22-2 S1C17F13 TeChniCal Manual (Rev. 1.0)
  • Page 208 Run in RAM, OSC1BCLK/1 Run in Flash, OSC1ACLK/1 Run in RAM, OSC1BCLK/2 Run in Flash, OSC1BCLK/2 Run in RAM, OSC1ACLK/1 Run in Flash, OSC1ACLK/2 Run in RAM, OSC1ACLK/2 Ta [°C] Ta [°C] Seiko epson Corporation S1C17F13 TeChniCal Manual 22-3 (Rev. 1.0)

  • Page 209: System Reset Controller (Src) Characteristics

    RST- POR&BOR reset request Indefinite (operating limit) POR/BOR reset request Note: When performing a power-on-reset again after the power is turned off, decrease the V voltage to 1 V or less. Seiko epson Corporation 22-4 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 210: Clock Generator (Clg) Characteristics

    – – µs Oscillation frequency CLGOSC3B.OSC3BFREQ[1:0] bits = 0x3 18.0 20.0 22.0 OSC3B CLGOSC3B.OSC3BFREQ[1:0] bits = 0x2 14.4 16.0 17.6 CLGOSC3B.OSC3BFREQ[1:0] bits = 0x1 10.8 12.0 13.2 CLGOSC3B.OSC3BFREQ[1:0] bits = 0x0 Seiko epson Corporation S1C17F13 TeChniCal Manual 22-5 (Rev. 1.0)

  • Page 211: Flash Memory Characteristics

    Programmed data is guaranteed to be – – times retained for 10 years. *1 Assumed that Erasing + Programming as count of 1. The count includes programming in the factory for shipment with ROM data programmed. Seiko epson Corporation 22-6 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 212: Input/Output Port (Pport) Characteristics

    Ta = 70 °C, Max. value Ta = 70 °C, Min. value –V = 2.0 V = 3.6 V = 2.0 V = 3.6 V 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Seiko epson Corporation S1C17F13 TeChniCal Manual 22-7 (Rev. 1.0)

  • Page 213: Supply Voltage Detector (Svd) Characteristics

    Invalid Valid Invalid Valid SVDEN SVD circuit current - power supply voltage characteristic Ta = 25 °C, SVDCTL.SVDC[4:0] bits = 0x0c, CLK_SVD = 32 kHz, Typ. value SVDCTL.SVDMD[1:0] bits = 0x0 Seiko epson Corporation 22-8 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 214: Uart (Uart) Characteristics

    (CPOL, CPHA) = (1, 0) or (0, 1) SPICLKn (CPOL, CPHA) = (1, 1) or (0, 0) SDIn SDOn Slave mode #SPISSn SPICLKn (CPOL, CPHA) = (0, 1) SPICLKn (CPOL, CPHA) = (1, 0) SDIn Hi-Z SDOn Seiko epson Corporation S1C17F13 TeChniCal Manual 22-9 (Rev. 1.0)
  • Page 215 – Write data hold time – – Read data setup time – – Read data hold time – – Read timing #PIOCE #PIORD PIOA[7:0] PIOD[7:0] Write timing #PIOCE #PIOWR PIOA[7:0] PIOD[7:0] Seiko epson Corporation 22-10 S1C17F13 TeChniCal Manual (Rev. 1.0)
  • Page 216 22 ELECTRICAL CHARACTERISTICS 22.13 EPD Timing Controller (EPD Tcon) Characteristics Refer to the EPD Timing Controller S1C17F13 Manual (separately attached sheet). 22.14 R/F Converter (RFC) Characteristics R/F converter characteristics change depending on conditions (board pattern, components used, etc.). Use these characteristic values as a reference and perform evaluation using the actual printed circuit board.
  • Page 217 The temperature detection circuit measures temperature inside the device. Depending on the use environment, the difference between the measured temperature and the ambient temperature may be increased. When using the measured temperature as the ambient temperature, prepare an appropriate conversion table according to the use environment. Seiko epson Corporation 22-12 S1C17F13 TeChniCal Manual (Rev. 1.0)
  • Page 218 * For recommended component values, refer to “Recommended Operating Conditions” in the “Electrical Characteristics” chapter. The C , and C capacitance values should be determined after performing matching evaluation of the resonator mounted on the printed circuit board actually used. Seiko epson Corporation S1C17F13 TeChniCal Manual 23-1 (Rev. 1.0)

  • Page 219: Package

    24 PACKAGE Package TQFP13-64pin package (Unit: mm) INDEX 0.17–0.27 0.09–0.2 0°–10° 0.3–0.75 Figure 24. 1 TQFP13-64pin Package Dimensions Seiko epson Corporation S1C17F13 TeChniCal Manual 24-1 (Rev. 1.0)

  • Page 220: Appendix A List Of Peripheral Circuit Control Registers

    – 5–4 CLKDIV[1:0] R/WP 3–2 – – 1–0 CLKSRC[1:0] R/WP 0x4042 CLGOSC 15–12 – – – (CLG Oscillation EXOSCSLPC Control Register) OSC3ASLPC OSC1SLPC OSC3BSLPC 7–4 – – EXOSCEN OSC3AEN OSC1EN OSC3BEN Seiko epson Corporation S1C17F13 TeChniCal Manual aP-a-1 (Rev. 1.0)

  • Page 221: 0X4052

    (ILVSVD) 0x4082 ITCLV1 15–11 – 0x00 – – (ITC Interrupt Level 10–8 ILV3[2:0] Real-time clock interrupt Setup Register 1) (ILVRTC) 7–3 – 0x00 – – 2–0 ILV2[2:0] Clock generator interrupt (ILVCLG) Seiko epson Corporation aP-a-2 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 222: 0X40A0-0X40A2

    3–2 – – 1–0 CLKSRC[1:0] R/WP 0x40a2 WDTCTL 15–10 – 0x00 – – (WDT Control NMIXRST R/WP Register) STATNMI 7–5 – – WDTCNTRST Always read as 0. 3–0 WDTRUN[3:0] R/WP – Seiko epson Corporation S1C17F13 TeChniCal Manual aP-a-3 (Rev. 1.0)

  • Page 223: 0X40C0-0X40C8

    (SVD Control 14–13 SVDSC[1:0] R/WP Writing takes effect when Register) the SVDCTL.SVDMD[1:0] bits are not 0x0. 12–8 SVDC[4:0] 0x00 R/WP – 7–4 SVDRE[3:0] R/WP – – 2–1 SVDMD[1:0] R/WP MODEN R/WP Seiko epson Corporation aP-a-4 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 224: 0X4160-0X416C

    7–0 P0IN[7:0] 0x00 Register) 0x4202 P0IOEN 15–8 P0IEN[7:0] 0x00 – (P0 Port Enable 7–0 P0OEN[7:0] 0x00 Register) 0x4204 P0RCTL 15–8 P0PDPU[7:0] 0x00 – (P0 Port Pull-up/down 7–0 P0REN[7:0] 0x00 Control Register) Seiko epson Corporation S1C17F13 TeChniCal Manual aP-a-5 (Rev. 1.0)
  • Page 225 5–4 P12MUX[1:0] 3–2 P11MUX[1:0] 1–0 P10MUX[1:0] 0x4220 P2DAT 15–8 P2OUT[7:0] 0x00 – (P2 Port Data 7–0 P2IN[7:0] Register) 0x4222 P2IOEN 15–8 P2IEN[7:0] 0x00 – (P2 Port Enable 7–0 P2OEN[7:0] 0x00 Register) Seiko epson Corporation aP-a-6 S1C17F13 TeChniCal Manual (Rev. 1.0)
  • Page 226 (P4 Port Function 7–4 – – Select Register) 3–2 P41MUX[1:0] 1–0 P40MUX[1:0] 0x42d0 PDDAT 15–11 – 0x00 – – (Pd Port Data 10–8 PDOUT[2:0] Register) 7–3 – 0x00 – 2–0 PDIN[2:0] Seiko epson Corporation S1C17F13 TeChniCal Manual aP-a-7 (Rev. 1.0)

  • Page 227: 0X4380-0X438E

    0x4386 UA0CTL 15–8 – 0x00 – – (UART Ch.0 Control 7–2 – 0x00 – Register) SFTRST MODEN 0x4388 UA0TXD 15–8 – 0x00 – – (UART Ch.0 Transmit 7–0 TXD[7:0] 0x00 Data Register) Seiko epson Corporation aP-a-8 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 228: 0X43A0-0X43Ac

    (T16 Ch.1 Interrupt 7–1 – 0x00 – Flag Register) UFIF Cleared by writing 1. 0x43ac T16_1INTE 15–8 – 0x00 – – (T16 Ch.1 Interrupt 7–1 – 0x00 – Enable Register) UFIE Seiko epson Corporation S1C17F13 TeChniCal Manual aP-a-9 (Rev. 1.0)

  • Page 229: 0X43B0-0X43Ba

    0x43c4 I2C0BR 15–8 – 0x00 – – (I2C Ch.0 Baud-Rate – – Register) 6–0 BRT[6:0] 0x7f 0x43c8 I2C0OADR 15–10 – 0x00 – – (I2C Ch.0 Own 9–0 OADR[9:0] 0x000 Address Register) Seiko epson Corporation aP-a-10 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 230: 0X5000-0X500E

    – – MULTIMD 1–0 CLKSRC[1:0] 0x5002 T16A0CTL 15–9 – 0x00 – – (T16A3 Counter Ch.0 PRUN Control Register) – – Read value is undefined. – 5–4 CCABCNT[1:0] CBUFEN TRMD PRESET MODEN Seiko epson Corporation S1C17F13 TeChniCal Manual aP-a-11 (Rev. 1.0)

  • Page 231: 0X5020-0X502E

    – (T16A3 Counter Ch.1 PRUN Control Register) – – Read value is undefined. – 5–4 CCABCNT[1:0] CBUFEN TRMD PRESET MODEN 0x5024 T16A1TC 15–0 T16ATC[15:0] 0x0000 – (T16A3 Counter Ch.1 Data Register) Seiko epson Corporation aP-a-12 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 232: 0X5180-0X5186

    (CT Interrupt Flag 7–4 – – Register) CT32HZIF Cleared by writing 1. CT8HZIF CT2HZIF CT1HZIF 0x5186 CTINTE 15–8 – 0x00 – – (CT Interrupt Enable 7–4 – – Register) CT32HZIE CT8HZIE CT2HZIE CT1HZIE Seiko epson Corporation S1C17F13 TeChniCal Manual aP-a-13 (Rev. 1.0)

  • Page 233: 0X5260-0X526C

    (SPI Ch.1 Interrupt 7–4 – – Flag Register) TENDIF H0/S0 Cleared by writing 1. RBFIF H0/S0 Cleared by reading the SPI1RXD register. TBEIF H0/S0 Cleared by writing to the SPI1TXD register. Seiko epson Corporation aP-a-14 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 234: 0X5280-0X528C

    MODEN 0x5294 SPI2TXD 15–8 – 0x00 – – (SPI Ch.2 Transmit 7–0 TXD[7:0] 0x00 Data Register) 0x5296 SPI2RXD 15–8 – 0x00 – – (SPI Ch.2 Receive 7–0 RXD[7:0] 0x00 Data Register) Seiko epson Corporation S1C17F13 TeChniCal Manual aP-a-15 (Rev. 1.0)

  • Page 235: 0X52E0-0X52Ea

    Flag and Status Reg- 7–1 – 0x00 – ister) ENDIF Cleared by writing 1. 0x5384 EPDINTE 15–8 – 0x00 – – (EPD Tcon Interrupt 7–1 – 0x00 – Enable Register) ENDIE Seiko epson Corporation aP-a-16 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 236: 0X5440-0X5450

    Flag Register) OVTCIF Cleared by writing 1. OVMCIF ESENBIF ESENAIF EREFIF 0x5450 RFC0INTE 15–8 – 0x00 – – (RFC Ch.0 Interrupt 7–5 – – Enable Register) OVTCIE OVMCIE ESENBIE ESENAIE EREFIE Seiko epson Corporation S1C17F13 TeChniCal Manual aP-a-17 (Rev. 1.0)

  • Page 237: 0X5460-0X5470

    Flag Register) OVTCIF Cleared by writing 1. OVMCIF ESENBIF ESENAIF EREFIF 0x5470 RFC1INTE 15–8 – 0x00 – – (RFC Ch.1 Interrupt 7–5 – – Enable Register) OVTCIE OVMCIE ESENBIE ESENAIE EREFIE Seiko epson Corporation aP-a-18 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 238: 0X54C0-0X54Ca

    0x00 – Enable Register) TEMIE 0xffff90 Debugger (DBG) Address Register name Bit name Initial Reset Remarks 0xffff90 DBRAM 31–24 – 0x00 – – (Debug RAM Base 23–0 DBRAM[23:0] 0x00 Register) 17c0 Seiko epson Corporation S1C17F13 TeChniCal Manual aP-a-19 (Rev. 1.0)

  • Page 239: Appendix B Power Saving

    • Using a resonator with lower C value decreases current consumption. However, these configurations may reduce the oscillation margin and increase the frequency error, therefore, be sure to perform matching evaluation using the actual printed circuit board. Seiko epson Corporation S1C17F13 TeChniCal Manual aP-B-1 (Rev. 1.0)

  • Page 240: Other Power Saving Methods

    Continuous operation mode (SVDCTL.SVDMD[1:0] bits = 0x0) always detects the power supply voltage, therefore, it increases current consumption. Set the supply voltage detector to intermittent operation mode or turn it on only when required. Seiko epson Corporation aP-B-2 S1C17F13 TeChniCal Manual (Rev. 1.0)
  • Page 241 (2) If a bypass capacitor is connected between V and V , connections between the V and V pins should be as short as possible. Seiko epson Corporation S1C17F13 TeChniCal Manual aP-C-1 (Rev. 1.0)

  • Page 242: Appendix C Mounting Precautions

    (2) Electromagnetically-induced noise from a solder iron when soldering In particular, during soldering, take care to ensure that the soldering iron GND (tip potential) has the same po- tential as the IC GND. Seiko epson Corporation aP-C-2 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 243: Appendix D Measures Against Noise

    • Execute the resending process via software after executing the receive error handler with a parity check. For details of the pin functions and the function switch control, see the “I/O Ports” chapter. For the UART con- trol and details of receive errors, see the “UART” chapter. Seiko epson Corporation S1C17F13 TeChniCal Manual aP-D-1 (Rev. 1.0)
  • Page 244 ; Flash read wait cycle Xld.a %r0, 0x00 ; 0x00 = No wait, 0x01 = 1 wait, or 0x02 = 2 wait ...(5) ld.b [%r1], %r0 ; [0x41b0] <= 0x00 ; ===== Main routine ========================================= Seiko epson Corporation S1C17F13 TeChniCal Manual aP-e-1 (Rev. 1.0)

  • Page 245: Appendix E Initialization Routine

    “intXX_handler” can be used for software interrupts. (3) The program code is written in the “.text” section. (4) Sets the stack pointer. (5) Sets the number of Flash memory read cycles. (See the “Memory and Bus” chapter.) Seiko epson Corporation aP-e-2 S1C17F13 TeChniCal Manual (Rev. 1.0)

  • Page 246: Revision History

    REVISION HISTORY Revision History Code No. Page Contents 412486300 New establishment...
  • Page 247 KOnG lTD. Unit 715-723, 7/F Trade Square, 681 Cheung Sha Wan Road, Kowloon, Hong Kong Phone: +852-2585-4600 Fax: +852-2827-4346 ePSOn TaiWan TeChnOlOGY & TRaDinG lTD. 14F, No. 7, Song Ren Road, Taipei 110, TAIWAN Phone: +886-2-8786-6688 Fax: +886-2-8786-6660 ePSOn SinGaPORe PTe., lTD.

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