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Epson S1C17001 Technical Manual

Cmos 16-bit single chip microcontroller.
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CMOS 16-BIT SINGLE CHIP MICROCONTROLLER
S1C17001
Technical Manual

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   Summary of Contents for Epson S1C17001

  • Page 1

    CMOS 16-BIT SINGLE CHIP MICROCONTROLLER S1C17001 Technical Manual...

  • Page 2

    No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not...

  • Page 3: Table Of Contents

    6.3.2 Interrupt Request from Peripheral Module and Interrupt Flag ......6-3 6.3.3 Interrupt Permission/Prohibition ............... 6-4 6.3.4 Processing for Multiple Interrupts ..............6-5 6.3.5 Interrupt Trigger Modes ..................6-6 6.3.6 S1C17 Core Interrupt Processing ..............6-8 6.4 NMI ..........................6-9 6.5 Software Interrupts ......................6-10 EPSON S1C17001 TECHNICAL MANUAL...

  • Page 4: Table Of Contents

    10.2 Input/Output Port Pin Function Selection (Port MUX) ..........10-2 10.3 Data Input/Output ......................10-3 10.4 Pull-up Control ......................10-4 10.5 Input Interface Level ....................10-5 10.6 P0 Port Chattering Filter Function ................10-6 10.7 Port Input Interrupt ....................... 10-7 EPSON S1C17001 TECHNICAL MANUAL...

  • Page 5: Table Of Contents

    0x4200: 8-bit Timer Input Clock Select Register (T8F_CLK) ..........12-11 0x4202: 8-bit Timer Reload Data Register (T8F_TR) ............... 12-12 0x4204: 8-bit Timer Counter Data Register (T8F_TC) ............. 12-13 0x4206: 8-bit Timer Control Register (T8F_CTL) ..............12-14 12.11 Precautions ....................... 12-16 EPSON S1C17001 TECHNICAL MANUAL...

  • Page 6: Table Of Contents

    15.7 Precautions ......................... 15-12 16 Stopwatch Timer (SWT) .....................16-1 16.1 Stopwatch Timer Overview ..................16-1 16.2 BCD Counters ......................16-2 16.3 Operation Clock ......................16-3 16.4 Stopwatch Timer Resetting ..................16-4 16.5 Stopwatch Timer RUN/STOP Control ................16-5 EPSON S1C17001 TECHNICAL MANUAL...

  • Page 7: Table Of Contents

    19.7 Control Register Details ....................19-10 0x4320: SPI Status Register (SPI_ST) ..................19-11 0x4322: SPI Transmit Data Register (SPI_TXD) ..............19-12 0x4324: SPI Receive Data Register (SPI_RXD) ............... 19-13 0x4326: SPI Control Register (SPI_CTL) ................. 19-14 19.8 Precautions ......................... 19-16 EPSON S1C17001 TECHNICAL MANUAL...

  • Page 8: Table Of Contents

    24.5 AC Characteristics ....................... 24-4 24.5.1 SPI AC Characteristics .................. 24-4 24.5.2 I C AC Characteristics ................... 24-4 24.5.3 External Clock Input AC Characteristics ............24-5 24.5.4 System AC Characteristics ................24-5 24.6 Oscillation Characteristics ................... 24-6 25 Package ........................25-1 EPSON S1C17001 TECHNICAL MANUAL...

  • Page 9: Table Of Contents

    Appendix B Power Saving .................... AP-25 B.1 Clock Control Power Saving ..................AP-25 Appendix C Mounting Precautions ................AP-28 Appendix D Initialization Routine ................. AP-31 Appendix E S1C17001 Mask ROM Code Development ..........AP-33 Appendix F Revision History ..................AP-34 EPSON S1C17001 TECHNICAL MANUAL...

  • Page 10: Overview

    It allows 8.2 MHz high-speed operation at an operating voltage of just 1.8 V, and executes single commands using a single clock with 16-bit RISC processing. 1.1 Features The main features of the S1C17001 are listed below. ● • ●Main (OSC3) oscillator circuit •...

  • Page 11: Block Diagram

    (P16, P07, P06) SIN, SOUT, SCLK PWM & capture UART EXCL3(P27), timer (P23–25) TOUT(P26) SDI, SDO, SPICLK Remote controller REMI(P04), (P20–22) REMO(P05) I/O port/ SDA, SCL P00–07, P10–17, I/O MUX (P14–15) P20–27, P30–33 Figure 1.2.1: Block diagram EPSON S1C17001 TECHNICAL MANUAL...

  • Page 12: Pins

    Bottom View Index Top View #TEST2 #TEST3 REMO #RESET EXCL1 EXCL2 REMI EXCL0 EXCL3 TOUT FOUT1 FOUT3 DSIO DST2 DCLK OSC1 SPICLK SCLK TEST0 #TEST4 OSC2 #SPISS #TEST1 OSC4 OSC3 #TEST5 SOUT Figure 1.3.1.1: Pinout diagram (WCSP-48pin) EPSON S1C17001 TECHNICAL MANUAL...

  • Page 13: Pin Descriptions

    46 V – – Power supply pin (GND) 47 LV – – Power supply pin (LV 48 V – – Power supply pin (GND) Note: Pins appearing in bold and functions indicated by “*” are default settings. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 14: S1c17 Core Features

    2 CPU 2 CPU The S1C17001 uses an S1C17 core as the core processor. The S1C17 core is an original Seiko Epson 16-bit RISC processor. It features low power consumption, high-speed operation, wide address space, main command single-clock execu- tion, and gate-saving design. It is ideal for use in controllers or sequencers, in which 8-bit CPUs are widely used.

  • Page 15: Cpu Registers

    2 CPU 2.2 CPU Registers The S1C17 core contains eight general purpose registers and three special registers. Special registers General purpose registers Bit 23 Bit 0 Bit 23 Bit 0 IL[2:0] Figure 2.2.1: Registers EPSON S1C17001 TECHNICAL MANUAL...

  • Page 16: Command Set

    General purpose register (32 bits, zero extension) ➔ Memory (*1) [imm7],%rs SP ➔ General purpose register %rd,%sp PC ➔ General purpose register %rd,%pc Stack (32 bits) ➔ General purpose register (*1) %rd,[%sp] %rd,[%sp]+ Stack pointer post-increment/post-decrement %rd,[%sp]- A pre-decrement function can be used %rd,-[%sp] EPSON S1C17001 TECHNICAL MANUAL...

  • Page 17

    NOT operation between general purpose registers (1 complement) not/c Supports conditional execution (/c: Executed when C = 1, /nc: Executed when not/nc C = 0) NOT operation for general purpose register and immediate (1 complement) %rd,sign7 EPSON S1C17001 TECHNICAL MANUAL...

  • Page 18

    *1: Command ld.a accesses 32-bit memory. When data is transferred from register to memory, 32 bits of data with the first 8 bits set to 0 are written to memory. When data is read from memory, the first 8 bits are ignored. *2: Coprocessor commands are reserved, since the S1C17001 does not include a coprocessor. EPSON...

  • Page 19

    Stack (with address post-increment) [%sp]+ Stack (with address post-decrement) [%sp]- Stack (with address pre-decrement) -[%sp] imm3 , imm5 , imm7 , imm13 Immediate without code (number indicates bit length) Immediate with code (number indicates bit length) sign7 , sign10 EPSON S1C17001 TECHNICAL MANUAL...

  • Page 20: Vector Table

    The boot address for starting program execution must be written at the top of the vector table after resetting. The S1C17001 vector table starts from address 0x8000. The vector table base address can be read from the TTBR (vector table base register) at address 0xffff80.

  • Page 21: Processor Information

    2 CPU 2.5 Processor Information The S1C17001 contains a processor ID register (0xffff84) to allow specification of the CPU core type by the appli- cation software. 0xffff84: Processor ID Register (IDIR) Register name Address Name Function Setting Init. R/W Remarks...

  • Page 22: Memory Map And Bus Control

    3 MEMORY MAP AND BUS CONTROL 3 Memory Map and Bus Control Figure 3.1 shows the S1C17001 memory map. Peripheral functions (Device size) reserved 0x5360~0x5fff Remote controller (8 bits) 0xff ffff 0x5340~0x535f Core I/O reserved area MISC register (8 bits)

  • Page 23: Bus Cycle

    • If a command is executed for an internal ROM area while accessing internal ROM and internal peripheral circuit area 2 (0x5000 onward) data • If a command is executed for an internal RAM area while accessing internal RAM area data EPSON S1C17001 TECHNICAL MANUAL...

  • Page 24: Internal Rom Area

    – – – 0 when being read. Control Register (8 bits) D2–0 FLCYC[2:0] ROM read access cycle FLCYC[2:0] Read cycle 0x3 R/W (MISC_FL) 0x7–0x5 reserved 1 cycle 5 cycles 4 cycles 3 cycles 2 cycles EPSON S1C17001 TECHNICAL MANUAL...

  • Page 25: Internal Ram Area

    Note: The last 64 bytes of the internal RAM (0x7c0 to 0x7ff) are reserved for on-chip debugging. This area should not be accessed by application programs when using debug functions (for exam- ple, during application development). It can be used for applications in mass-produced products that do not require debugging. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 26: Internal Peripheral Circuit Area

    • 8-bit OSC1 timer (T8OSC1, 8-bit device) • Input/output port & port MUX (P, 8-bit device) • PWM & capture timer (T16E, 16-bit device) • MISC register (MISC, 8-bit device) • Remote controller (REMC, 8-bit device) EPSON S1C17001 TECHNICAL MANUAL...

  • Page 27: I/o Map

    C module enable (16-bit device) 0x4342 I2C_CTL C Control Register C control and transfer status display 0x4344 I2C_DAT C Data Register Transfer data 0x4346 I2C_ICTL C Interrupt Control Register C interrupt control 0x4348 to 0x435f – – Reserved EPSON S1C17001 TECHNICAL MANUAL...

  • Page 28

    P1 Port Function Select Register P1 port function selection 0x52a2 P2_PMUX P2 Port Function Select Register P2 port function selection 0x52a3 P3_PMUX P3 Port Function Select Register P3 port function selection 0x52a4 to 0x52bf – – Reserved EPSON S1C17001 TECHNICAL MANUAL...

  • Page 29

    Transfer bit 0x5345 REMC_LCNT REMC Length Counter Register Transfer data length setting 0x5346 REMC_IMSK REMC Interrupt Mask Register Interrupt mask setting 0x5347 REMC_IFLG REMC Interrupt Flag Register Interrupt occurrence status display/reset 0x5348 to 0x535f – – Reserved EPSON S1C17001 TECHNICAL MANUAL...

  • Page 30: Core I/o Reserved Area

    Debugging RAM base address display For more information on TTBR, refer to “2.4 Vector Table”; and for more information on IDIR, refer to “2.5 Pro- cessor Information.” For more information on DBRAM, refer to “22 On-chip Debugging (DBG).” EPSON S1C17001 TECHNICAL MANUAL...

  • Page 31

    3 MEMORY MAP AND BUS CONTROL This page intentionally left blank. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 32: Power Supply Voltage

    4 POWER SUPPLY VOLTAGE 4 Power Supply Voltage The S1C17001 operation power supply voltages are given below. Core voltage (LV ): 1.65 V to 2.7 V I/O voltage (HV ): 1.65 V to 3.6 V Supply voltages within the respective ranges to LV...

  • Page 33

    4 POWER SUPPLY VOLTAGE This page intentionally left blank. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 34: Initial Reset

    Initial resetting is possible by inputting external Low level to the #RESET pin. To initialize the S1C17001 reliably, the #RESET pin must be maintained at Low level for at least the specified du- ration after the power supply voltage rises. (Refer to “24.5 AC Characteristics.”) Initial resetting is canceled if the #RESET input changes from Low to High, and the CPU begins reset interrupt processing.

  • Page 35: P0 Port Key-entry Reset

    5.1.3 Reset by Watchdog Timer The S1C17001 incorporates a watchdog timer to detect runaway CPU. If the watchdog timer is not reset by soft- ware every 4 seconds (with this failure indicating a runaway CPU), the timer overflows, generating an NMI or re- set.

  • Page 36: Initial Reset Sequence

    SLEEP cancellation and command ex- ecution. OSC3 clock #RESET Reset cancellation Reset cancellation Internal reset cancellation Internal data request Boot vector Internal data address Oscillation Boot operation start stabilization standby time Figure 5.2.1: Sequence of operations after initial reset cancellation EPSON S1C17001 TECHNICAL MANUAL...

  • Page 37: Initial Settings At Initial Resetting

    The internal peripheral circuits are initialized in accordance with their particular specifications. They should be reset via software, if necessary. For detailed information on initial values after initial resetting, refer to the I/O register list in the Appendix or the respective peripheral circuit descriptions. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 38: Itc Configuration

    6 INITERRUPT CONTROLLER 6 Interrupt Controller 6.1 ITC Configuration The S1C17001 features the following 14 different types of hardware interrupts: 1. P00 to P07 input interrupt (8 types) 2. P10 to P17 input interrupt (8 types) 3. Stopwatch timer interrupt (3 types) 4.

  • Page 39

    The vector table contains the vectors (processing routine start addresses) for interrupt processing routines. When an interrupt occurs, the S1C17 core reads the vector corresponding to the interrupt and executes that processing routine. The S1C17001 vector table starts from address 0x8000. The vector table base address can be read from the TTBR register (0xffff80).

  • Page 40: Maskable Interrupt Control

    1. These interrupt flags are reset when the interrupt source sets the interrupt signal to inac- tive. Refer to the interrupt source module section for detailed information on the conditions under which interrupt fac- tors arise and individual module interrupt settings are made. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 41: Interrupt Permission/prohibition

    1, in addition to the interrupt enable bit. The S1C17 core will not accept maskable interrupt requests if the IE bit is set to 0. In this case, interrupt requests from the ITC will be retained and accepted after the IE bit is set to 1. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 42: Processing For Multiple Interrupts

    If an interrupt factor of higher priority occurs while the ITC outputs an interrupt request signal to the S1C17 core (before acceptance by the S1C17 core), the ITC alters the vector number and interrupt level signal to the setting de- tails of the most recent interrupt. The immediately preceding interrupt is held. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 43: Interrupt Trigger Modes

    Reset when software writes 1 to interrupt flag Figure 6.3.5.1: Pulse trigger mode Note: The S1C17001 interrupts listed below are in pulse trigger mode. If an interrupt occurs, reset the interrupt flag IIFTx (to 1) within the interrupt processing routine.

  • Page 44

    Interrupt signal set to inactive by interrupt source Figure 6.3.5.2: Level trigger mode Note: The S1C17001 interrupts listed below are in level trigger mode. The interrupt flag within pe- ripheral modules must be reset (to 1) within the interrupt processing routine rather than EIFTx •...

  • Page 45: S1c17 Core Interrupt Processing

    Ending interrupt processing routines using a reti command returns the PSR to the state before the interrupt. The program resumes processing following the command being executed at the time the interrupt occurred via the next branch. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 46

    6 INITERRUPT CONTROLLER 6.4 NMI The S1C17001 can generate NMIs (non-maskable interrupts) using the watchdog timer. The vector number for NMIs is 2, and the vector address is set in the vector table initial address + 8 bytes. These interrupts take prece- dence over other interrupt factors and are accepted unconditionally by the S1C17 core.

  • Page 47: Software Interrupts

    (0 to 31) is specified by the operand immediate imm5. With the intl command, imm3 can be used to specify an interrupt level (0 to 7) for the PSR IL fields. Details of the processor interrupt processing are the same as for when an interrupt generated by hardware occurs. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 48: Halt And Sleep Mode Cancellation By Interrupt Factors

    The interrupt factors capable of starting the CPU and specific program execution details after CPU startup (whether to branch into an interrupt processing routine) depend on the clock states in HALT and SLEEP modes. For more information, refer to “B.1 Clock Control Power Saving” in Appendix B. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 49: Control Register Details

    Sets SPI and I C interrupt levels. The ITC registers are described in detail below. These are 16-bit registers. Note: When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 50: X4300: Interrupt Flag Register (itc_iflg)

    UART interrupt: Transmit buffer empty/Receive buffer full/Receive error IIFT5 (D13) Remote controller interrupt: Data length counter underflow/Input rise-up/Input drop- IIFT6 (D14) SPI interrupt: Transmit buffer empty/Receive buffer full IIFT7 (D15) C interrupt: Transmit buffer empty/Receive buffer full EPSON S1C17001 TECHNICAL MANUAL...

  • Page 51

    Interrupt flags set to level trigger must be reset by the control register within the peripheral module. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 52: X4302: Interrupt Enable Register (itc_en)

    UART interrupt: Transmit buffer empty/Receive buffer full/Receive error IIEN5 (D13) Remote controller interrupt: Data length counter underflow/Input rise-up/Input drop- IIEN6 (D14) SPI interrupt: Transmit buffer empty/Receive buffer full IIEN7 (D15) C interrupt: Transmit buffer empty/Receive buffer full EPSON S1C17001 TECHNICAL MANUAL...

  • Page 53: X4304: Itc Control Register (itc_ctl)

    (16 bits) ITEN ITC enable 1 Enable 0 Disable (ITC_CTL) D[15:1] Reserved ITEN: ITC Enable Bit Permits interrupt control using the ITC. 1 (R/W): Permitted 0 (R/W): Prohibited (default) Set to 1 before using the ITC. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 54: X4306: External Interrupt Level Setup Register 0 (itc_elv0)

    0x0 R/W D[15:13] Reserved EITG1: P1 Port Interrupt Trigger Mode Select Bit Selects P1 port interrupt trigger mode. This should be set to 1 for the S1C17001. 1 (R/W): Level trigger mode 0 (R/W): Pulse trigger mode (default) In pulse trigger mode, the ITC samples interrupt signals using system clock rising edges. When the pulse High period is detected, the ITC sets the interrupt flag (EIFTx) to 1 and stops sampling that inter- rupt signal.

  • Page 55: X4308: External Interrupt Level Setup Register 1 (itc_elv1)

    0x0 R/W D[15:13] Reserved EITG3: Clock Timer Interrupt Trigger Mode Select Bit Selects clock timer interrupt trigger mode. This should be set to 1 for the S1C17001. 1 (R/W): Level trigger mode 0 (R/W): Pulse trigger mode (default) Refer to the ITC_ELV0 register (0x4306) EITG1 (D12) description.

  • Page 56: X430a: External Interrupt Level Setup Register 2 (itc_elv2)

    D[15:5] Reserved EITG4: 8-bit OSC1 Timer Interrupt Trigger Mode Select Bit Selects 8-bit OSC1 timer interrupt trigger mode. This should be set to 1 for the S1C17001. 1 (R/W): Level trigger mode 0 (R/W): Pulse trigger mode (default) Refer to the ITC_ELV0 register (0x4306) EITG1 (D12) description.

  • Page 57: X430c: External Interrupt Level Setup Register 3 (itc_elv3)

    D[15:13] Reserved EITG7: PWM & Capture Timer Interrupt Trigger Mode Select Bit Selects PWM & capture timer interrupt trigger mode. This should be set to 1 for the S1C17001. 1 (R/W): Level trigger mode 0 (R/W): Pulse trigger mode (default) Refer to the ITC_ELV0 register (0x4306) EITG1 (D12) description.

  • Page 58: X430e: Internal Interrupt Level Setup Register 0 (itc_ilv0)

    The immediately preceding interrupt is held. D[7:3] Reserved D[2:0] IILV0[2:0]: 8-bit Timer Interrupt Level Bits Set the 8-bit timer interrupt level (0 to 7). (Default: 0) Refer to the IILV1[2:0] (D[10:8]) description. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 59: X4310: Internal Interrupt Level Setup Register 1 (itc_ilv1)

    Refer to the ITC_ILV0 register (0x430e) IILV1[2:0] (D[10:8]) description. D[7:3] Reserved D[2:0] IILV2[2:0]: 16-bit Timer Ch.1 Interrupt Level Bits Set the 16-bit timer Ch.1 interrupt level (0 to 7). (Default: 0) Refer to the ITC_ILV0 register (0x430e) IILV1[2:0] (D[10:8]) description. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 60: X4312: Internal Interrupt Level Setup Register 2 (itc_ilv2)

    Refer to the ITC_ILV0 register (0x430e) IILV1[2:0] (D[10:8]) description. D[7:3] Reserved D[2:0] IILV4[2:0]: UART Interrupt Level Bits Set the UART interrupt level (0 to 7). (Default: 0) Refer to the ITC_ILV0 register (0x430e) IILV1[2:0] (D[10:8]) description. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 61: X4314: Internal Interrupt Level Setup Register 3 (itc_ilv3)

    Refer to the ITC_ILV0 register (0x430e) IILV1[2:0] (D[10:8]) description. D[7:3] Reserved D[2:0] IILV6[2:0]: SPI Interrupt Level Bits Set the SPI interrupt level (0 to 7). (Default: 0) Refer to the ITC_ILV0 register (0x430e) IILV1[2:0] (D[10:8]) description. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 62: Precautions

    • To prevent the recurrence of interrupts due to the same interrupt factor, always reset the interrupt flag before per- mitting interrupts, resetting PSR, or executing the reti command. • The S1C17001 interrupts listed below are in level trigger mode. - P0 port interrupt...

  • Page 63

    6 INITERRUPT CONTROLLER This page intentionally left blank. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 64: Oscillator Circuit (osc)

    7 Oscillator Circuit (OSC) 7.1 OSC Module Configuration The S1C17001 incorporates two internal oscillator circuits (OSC3 and OSC1). The OSC3 oscillator circuit gener- ates the main clock (max. 8.2 MHz) for high-speed operation of the S1C17 core and peripheral circuits. The OSC1 oscillator circuit generates a sub-clock (typ.

  • Page 65: Osc3 Oscillator Circuit

    ∗ OSC3EN: OSC3 Enable Bit in the Oscillation Control (OSC_CTL) Register (D0/0x5061) After initial resetting, OSC3EN is set to 1 and the OSC3 oscillator circuit is on. Since the OSC3 clock is used as the system clock, the S1C17 core begins operating using the OSC3 clock. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 66

    Note: The OSC3 oscillation start time depends on the oscillator and externally connected compo- nents. The time should be set with an adequate oscillation stabilization wait time. Refer to the typical oscillation start times specified in “24 Electrical Characteristics.” EPSON S1C17001 TECHNICAL MANUAL...

  • Page 67: Osc1 Oscillator Circuit

    OSC1 oscillation—for example, when power is first turned on, on awaking from SLEEP, or when the OSC1 oscillation circuit is turned on via software. The OSC1 clock does not feed the system for a period of 256 cycles after the start of oscillation. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 68: System Clock Switching

    The time should be set with an adequate oscillation stabilization wait time. Refer to the typical oscillation start times specified in “24 Electrical Characteristics.” • OSC1 oscillation cannot be stopped before switching the system clock to OSC3. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 69: Bit Osc1 Timer Clock Control

    8-bit OSC1 timer. Stop the clock feed to reduce power consumption if 8-bit OSC1 timer operation is not required. ∗ T8O1CE: T8OSC1 Clock Enable Bit in the T8OSC1 Clock Control (OSC_T8OSC1) Register (D0/0x5065) EPSON S1C17001 TECHNICAL MANUAL...

  • Page 70: Clock External Output (fout3, Fout1)

    ∗ FOUT3E: FOUT3 Output Enable Bit in the FOUT Control (OSC_FOUT) Register (D1/0x5064) FOUT3E FOUT3 output (P30) Figure 7.6.2: FOUT3 output Note: Since the FOUT3 signal is asynchronized with FOUT3E writing, switching output on or off will generate certain hazards. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 71

    ∗ FOUT1E: FOUT1 Output Enable Bit in the FOUT Control (OSC_FOUT) Register (D1/0x5064) FOUT1E FOUT1 output (P13) Figure 7.6.3: FOUT1 output Note: Since the FOUT1 signal is asynchronized with FOUT1E writing, switching output on or off will generate certain hazards. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 72: Reset And Nmi Input Noise Filters

    This means the pulse width must be at least 16 cycles of the system clock to input as a valid signal. Note: • All noise filters should normally be enabled. • The S1C17001 does not feature external NMI input pins, but the watchdog timer NMI re- quest signal passes through these filters.

  • Page 73

    8-bit OSC1 timer clock setting The OSC module registers are described in detail below. These are 8-bit registers. Note: When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 74: X5060: Clock Source Select Register (osc_src)

    OSC3 stopped to reduce power consumption. Note: If the system clock is switched from OSC3 to OSC1 immediately after starting OSC1 oscilla- tion, the system clock will stop until the OSC1 clock starts up (for the OSC1 clock 256-cycle period). EPSON S1C17001 TECHNICAL MANUAL...

  • Page 75: X5061: Oscillation Control Register (osc_ctl)

    OSC3EN: OSC3 Enable Bit Permits or prohibits OSC3 oscillator circuit operation. 1 (R/W): Permitted (on) (default) 0 (R/W): Prohibited (off) Note: The OSC3 oscillator circuit cannot be stopped if the OSC3 clock is being used as the system clock. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 76: X5062: Noise Filter Enable Register (osc_nfen)

    S1C17 core. Pulses having widths of less than 16 cycles are filtered out as noise. This should normally be enabled. Note: The S1C17001 does not feature external NMI input pins, but the watchdog timer NMI request signal passes through these filters.

  • Page 77: X5064: Fout Control Register (osc_fout)

    1 to P13MUX (D3/P1_PMUX register) if use is required for FOUT1 output. ∗ P13MUX: P13 Port Function Select Bit in the P1 Port Function Select (P1_PMUX) Register (D3/0x52a1) EPSON S1C17001 TECHNICAL MANUAL...

  • Page 78: X5065: T8osc1 Clock Control Register (osc_t8osc1)

    The T8O1CE default setting is 0, which stops the clock feed. Setting T8O1CE to 1 sends the clock selected by the above bit to the 8-bit OSC1 timer. Stop the clock feed to reduce power consumption if 8-bit OSC1 timer operation is not required. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 79

    • The OSC1 oscillator circuit cannot be stopped if the OSC1 clock is being used as the system clock. • Since the FOUT3/FOUT1 signal is asynchronized with FOUT3E/FOUT1E writing, switching output on or off will generate certain hazards. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 80: Clock Generator (clg)

    Division ratio selection On/off control Figure 8.1.1: CLG module configuration To reduce power consumption, control the clock in conjunction with processing and use standby mode. For more information on reducing power consumption, refer to “Appendix B: Power Saving.” EPSON S1C17001 TECHNICAL MANUAL...

  • Page 81: Cpu Core Clock (cclk) Control

    Executing the slp command suspends system clock feed to the CLG, thereby halting the CCLK feed as well. Clearing SLEEP mode with an external interrupt restarts the system clock feed and the CCLK feed. For more information on system clock control, refer to “7. Oscillator Circuit (OSC).” EPSON S1C17001 TECHNICAL MANUAL...

  • Page 82: Peripheral Module Clock (pclk) Control

    With the exception of control register access, the clock timer, stopwatch timer, watchdog timer, and 8-bit OSC1 timer operate using the OSC1 division clock. Stopping the PCLK prevents read/write access to/from the control register, but operation will continue. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 83

    CCLK division ratio setting The CLG module registers are described in detail below. These are 8-bit registers. Note: When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 84: X5080: Pclk Control Register (clg_pclk)

    PCLK is not required after setting the control register to start operations. • Clock timer • Stopwatch timer • Watchdog timer • 8-bit OSC1 timer Note: Do not set PCKEN[1:0] to 0x2 or 0x1, since doing so will stop the operation of certain pe- ripheral modules. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 85: X5081: Cclk Control Register (clg_cclk)

    Select the gear ratio for reducing system clock speed and set the CCLK clock speed for operating the S1C17 core. To reduce power consumption, operate the S1C17 core using the slowest possible clock speed. Table 8.4.3: CCLK gear ratio selection CCLKGR[1:0] Gear ratio (Default: 0x0) EPSON S1C17001 TECHNICAL MANUAL...

  • Page 86

    • 8-bit OSC1 timer (2) Do not set PCKEN[1:0] (D[1:0]/CLG_PCLK register) to 0x2 or 0x1, since doing so will stop the operation of certain peripheral modules. ∗ PCKEN[1:0]: PCLK Enable Bits in the PCLK Control (CLG_PCLK) Register (D[1:0]/0x5080) EPSON S1C17001 TECHNICAL MANUAL...

  • Page 87

    8 CLOCK GENERATOR (CLG) This page intentionally left blank. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 88: Prescaler (psc)

    9. Prescaler (PSC) 9.1 Prescaler Configuration The S1C17001 incorporates a prescaler to generate a clock for timer operations. The prescaler generates 15 differ- ent frequencies by dividing the PCLK clock fed from the clock generator into 1/1 to 1/16K. The peripheral modules to which the clock is fed include clock selection registers enabling selection of one as a count or operation clock.

  • Page 89

    0 (R/W): Stop (default) Write 1 to PRUN to operate the prescaler. Write 0 to PRUN to stop the prescaler. To reduce current con- sumption, stop the prescaler if the timer and interface module are already stopped. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 90

    9 PRESCALER (PSC) 9.3 Precautions PCLK must be fed from the clock generator to use the prescaler. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 91

    9 PRESCALER (PSC) This page intentionally left blank. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 92: Input/output Port (p)

    10 Input/Output Port (P) 10.1 Input/Output Port Configuration The S1C17001 includes 28 input/output ports (P0[7:0], P1[7:0], P2[7:0], P3[3:0]) to allow software switching of input/output direction. These share internal peripheral module input/output pins (with certain exceptions), but pins not used for peripheral modules can be used as general purpose input/output ports.

  • Page 93

    For information on functions other than the input/output ports, refer to the discussion of the peripheral modules in- dicated in parentheses. The sections below discuss port functions with the pins set as general purpose input/output ports. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 94: Data Input/output

    ∗ P2OUT[7:0]: P2[7:0] Port Output Data Bits in the P2 Port Output Data (P2_OUT) Register (D[7:0]/0x5221) ∗ P3OUT[3:0]: P3[3:0] Port Output Data Bits in the P3 Port Output Data (P3_OUT) Register (D[3:0]/0x5231) Writing to PxOUT[7:0] is possible without affecting pin status, even in input mode. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 95: Pull-up Control

    The wait time set should be a value not less than that calcu- lated from the following equation. Wait time = R x (C + load capacitance on board) x 1.6 [s] : pull-up resistance maximum value : pin capacitance maximum value EPSON S1C17001 TECHNICAL MANUAL...

  • Page 96: Input Interface Level

    10 INPUT/OUTPUT PORT (P) 10.5 Input Interface Level The S1C17001 input interface level is pegged to the CMOS mute level. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 97: P0 Port Chattering Filter Function

    Since input interrupts will malfunction under these conditions, the input signal rise- up/drop-off time should normally be set to 25 ns or less. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 98: Port Input Interrupt

    ∗ P1EDGE[7:0]: P1[7:0] Port Interrupt Edge Select Bits in the P1 Port Interrupt Edge Select (P1_EDGE) Register (D[7:0]/0x5216) Setting PxEDGE[7:0] to 1 generates port input interrupts at the input signal falling edge. Setting it to 0 (default) generates interrupts at the rising edge. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 99

    • The port interrupt has a higher set interrupt level than the PSR IL (interrupt level). • No other interrupt factors having higher precedence (e.g., NMI) are present. For more information on these interrupt control registers and procedures for when an interrupt occurs, refer to “6 Interrupt Controller (ITC).” EPSON S1C17001 TECHNICAL MANUAL...

  • Page 100

    10 INPUT/OUTPUT PORT (P) Interrupt vector The port interrupt vector numbers and vector addresses are as shown below. Table 10.7.2: Port interrupt vectors Port Vector number Vector address 4 (0x04) 0x8010 5 (0x05) 0x8014 EPSON S1C17001 TECHNICAL MANUAL...

  • Page 101

    P3 port function selection The input/output port registers are described in detail below. These are 8-bit registers. Note: When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 102: X5200/0x5210/0x5220/0x5230: Px Port Input Data Registers (px_in)

    PxIN[7:0] correspond directly to the Px[7:0] pins and read the pin voltage level regardless of input/out- put mode. 1 is read when the pin voltage is High; 0 is read when the voltage is Low. Writing operations to the read-only PxIN[7:0] are disabled. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 103: X5201/0x5211/0x5221/0x5231: Px Port Output Data Registers (px_out)

    PxOUT[7:0] correspond directly to the Px[7:0] pins and output data from the port pin as written. Setting the data bit to 1 sets the port pin to High; setting it to 0 sets it to Low. Port data can also be written in input mode. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 104: X5202/0x5212/0x5222/0x5232: Px Port I/o Direction Control Registers (px_io)

    PxIO[7:0] are the input/output direction selection bits corresponding directly to the Px[7:0] ports. Set- ting to 1 selects output mode, while setting to 0 selects input mode. The peripheral module function determines the input/output direction for when a pin is used for peripheral modules. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 105: X5203/0x5213/0x5223/0x5233: Px Port Pull-up Control Registers (px_pu)

    Wait time = R x (C + load capacitance on board) x 1.6 [s] : pull-up resistance maximum value : pin capacitance maximum value EPSON S1C17001 TECHNICAL MANUAL...

  • Page 106: X5205/5215: Px Port Interrupt Mask Registers (px_imsk)

    Setting PxIE[7:0] to 1 permits the corresponding interrupt, while setting to 0 blocks interrupts. Status changes for the input pin with interrupt blocked do not affect interrupt occurrence. To enable interrupt generation, the ITC P0 and P1 port interrupt enable bits must also be set to permit interrupts. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 107: X5206/5216: Px Port Interrupt Edge Select Registers (px_edge)

    Select the input signal edge for generating P0[7:0] and P1[7:0] port interrupts. 1 (R/W): Falling edge 0 (R/W): Rising edge (default) Port interrupts are generated at the input signal falling edge if PxEDGE[7:0] are set to 1 and at the ris- ing edge if set to 0. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 108: X5207/5217: Px Port Interrupt Flag Registers (px_iflg)

    PxIE[7:0] (Px_IMSK register). ∗ P0IE[7:0]: P0[7:0] Port Interrupt Enable Bits in the P0 Port Interrupt Mask (P0_IMSK) Register (D[7:0]/0x5205) ∗ P1IE[7:0]: P1[7:0] Port Interrupt Enable Bits in the P1 Port Interrupt Mask (P1_IMSK) Register (D[7:0]/0x5215) EPSON S1C17001 TECHNICAL MANUAL...

  • Page 109: X5208: P0 Port Chattering Filter Control Register (p0_chat)

    Since input interrupts will malfunction under these conditions, the input signal rise-up/drop-off time should normally be set to 25 ns or less. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 110: X5209: P0 Port Key-entry Reset Configuration Register (p0_krst)

    P0 port key-entry reset function. • The P0 port key entry reset function is disabled on initial resetting and cannot be used for resetting at power-on. • The P0 port key-entry reset function cannot be used in SLEEP state. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 111: X52a0: P0 Port Function Select Register (p0_pmux)

    D[7:6] Reserved P05MUX: P05 Port Function Select Bit 1 (R/W): REMO (REMC) 0 (R/W): P05 port (default) P04MUX: P04 Port Function Select Bit 1 (R/W): REMI (R EMC) 0 (R/W): P04 port (default) D[3:0] Reserved EPSON S1C17001 TECHNICAL MANUAL...

  • Page 112: X52a1: P1 Port Function Select Register (p1_pmux)

    0 (R/W): P15 port (default) P14MUX: P14 Port Function Select Bit 1 (R/W): SDA (I2C) 0 (R/W): P14 port (default) P13MUX: P13 Port Function Select Bit 1 (R/W): FOUT1 (OSC) 0 (R/W): P13 port (default) D[2:0] Reserved EPSON S1C17001 TECHNICAL MANUAL...

  • Page 113: X52a2: P2 Port Function Select Register (p2_pmux)

    1 (R/W): SPICLK (SPI) 0 (R/W): P22 port (default) P21MUX: P21 Port Function Select Bit 1 (R/W): SDO (SPI) 0 (R/W): P21 port (default) P20MUX: P20 Port Function Select Bit 1 (R/W): SDI (SPI) 0 (R/W): P20 port (default) EPSON S1C17001 TECHNICAL MANUAL...

  • Page 114: X52a3: P3 Port Function Select Register (p3_pmux)

    1 (R/W): P32 port 0 (R/W): DST2 (DBG) (default) P31MUX: P31 Port Function Select Bit 1 (R/W): P31 port 0 (R/W): DCLK (DBG) (default) P30MUX: P30 Port Function Select Bit 1 (R/W): FOUT3 (OSC) 0 (R/W): P30 port (default) EPSON S1C17001 TECHNICAL MANUAL...

  • Page 115

    P0 port key-entry reset function. • The P0 port key entry reset function is disabled on initial resetting and cannot be used for resetting at power- • The P0 port key-entry reset function cannot be used in SLEEP state. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 116: Bit Timer (t16)

    11 16-bit Timer (T16) 11.1 16-bit Timer Overview The S1C17001 incorporates a 3-channel 16-bit timer (T16). The 16-bit timer consists of a 16-bit presettable down counter and a 16-bit reload data register holding the preset values. The timer counts down from the initial value set in the reload data register and outputs an underflow signal when the counter underflows.

  • Page 117: Bit Timer Operating Modes

    Note: • The prescaler must run before operating the 16-bit timer in internal clock mode. • Make sure the 16-bit timer count is halted before changing count clock settings. For detailed information on the prescaler control, see “9 Prescaler (PSC).” EPSON S1C17001 TECHNICAL MANUAL...

  • Page 118: External Clock Mode

    The 16-bit timer does not use the prescaler in this mode. If no other peripheral modules use the prescaler clock, the prescaler can be stopped to reduce current consumption. (The prescaler clock is used for P0 port chattering filter- ing.) EPSON S1C17001 TECHNICAL MANUAL...

  • Page 119: Pulse Width Measurement Mode

    Example 2: Detecting pulses over specified width Internal count clock PRUN External input signal n-1 n-2 n-3 0x2 0x1 0x0 Counter (CKACTV = 1) Underflow interrupt Figure 11.2.3.1: Pulse width measurement mode count operation EPSON S1C17001 TECHNICAL MANUAL...

  • Page 120: Count Mode

    Note that the timer presets the reload data register value to the coun- ter, then stops after an underflow has occurred. The 16-bit timer should be set to this mode to set a specific wait time or for pulse width measurement. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 121: Bit Timer Reload Register And Underflow Cycle

    The underflow cycle can be calculated as follows: TR + 1 clk_in Underflow interval = ——— [s] Underflow cycle = ——— [Hz] clk_in TR + 1 clk_in: Count clock (prescaler output clock) frequency [Hz] Reload data (0 to 65535) EPSON S1C17001 TECHNICAL MANUAL...

  • Page 122: Bit Timer Reset

    The 16-bit timer is reset by writing 1 to PRESER (D1/T16_CTLx register). The reload data is preset and the counter is initialized. ∗ PRESER: Timer Reset Bit in the 16-bit Timer Ch.x Control (T16_CTLx) Register (D1/0x4226/0x4246/0x4266) EPSON S1C17001 TECHNICAL MANUAL...

  • Page 123: Bit Timer Run/stop Control

    In Pulse width measurement mode, the timer counts only while PRUN is set to 1 and the external input signal is at the specified active level. When the external input signal becomes inactive, the 16-bit timer stops counting and re- tains the counter value until the next active level input. (See Figure 11.2.3.1.) EPSON S1C17001 TECHNICAL MANUAL...

  • Page 124: Bit Timer Output Signal

    Use the following equations to calculate the reload data register value for obtaining the desired transfer rate: clk_in TR = ———— - 1 bps × 2 clk_in TR = ———— - 1 bps × 4 clk_in: Count clock (prescaler output clock) frequency [Hz] Reload data (0 to 65535) bps: Transfer rate (bit/s) EPSON S1C17001 TECHNICAL MANUAL...

  • Page 125: Bit Timer Interrupts

    The timer interrupt vector numbers and vector addresses are listed below. Table 11.8.2: Timer interrupt vectors Timer channel Vector number Vector address Timer Ch.0 13 (0x0d) 0x8034 Timer Ch.1 14 (0x0e) 0x8038 Timer Ch.2 15 (0x0f) 0x803c EPSON S1C17001 TECHNICAL MANUAL...

  • Page 126

    Timer mode setting and timer RUN/STOP The 16-bit timer registers are described in detail below. These are 16-bit registers. Note: When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 127: X4220/0x4240/0x4260: 16-bit Timer Ch.x Input Clock Select Registers (t16_clkx)

    DF[3:0] Prescaler output clock Reserved PCLK-1/128 PCLK-1/16384 PCLK-1/64 PCLK-1/8192 PCLK-1/32 PCLK-1/4096 PCLK-1/16 PCLK-1/2048 PCLK-1/8 PCLK-1/1024 PCLK-1/4 PCLK-1/512 PCLK-1/2 PCLK-1/256 PCLK-1/1 (Default: 0x0) Note: Make sure the 16-bit timer count is halted before changing count clock settings. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 128: X4222/0x4242/0x4262: 16-bit Timer Ch.x Reload Data Registers (t16_trx)

    This means this reload value and the input clock frequency determine the time elapsed from the point at which the timer starts until the underflow occurs (or between underflows). The time determined is used to obtain the desired wait time, the intervals between periodic interrupts, and the programmable serial interface transfer clock. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 129: X4224/0x4244/0x4264: 16-bit Timer Ch.x Counter Data Registers (t16_tcx)

    0x4244: 16-bit Timer Ch.1 Counter Data Register (T16_TC1) 0x4264: 16-bit Timer Ch.2 Counter Data Register (T16_TC2) D[15:0] TC[15:0]: 16-bit Timer Counter Data Reads out the counter data. (Default: 0x0) This register is read-only and cannot be written to. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 130: X4226/0x4246/0x4266: 16-bit Timer Ch.x Control Registers (t16_ctlx)

    This enables inter- rupt generation and input pulse width measurements for pulse inputs of the specified width or greater. D[7:5] Reserved EPSON S1C17001 TECHNICAL MANUAL...

  • Page 131

    0 (R/W): Stop (default) The timer starts counting when PRUN is written as 1 and stops when written as 0. When the timer is stopped, the counter data is retained until reset or until the next RUN state. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 132

    11 16-BIT TIMER (T16) 11.10 Precautions • The prescaler must run before the 16-bit timer. • Set the count clock and count mode only while the 16-bit timer count is stopped. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 133

    11 16-BIT TIMER (T16) This page intentionally left blank. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 134: Bit Timer (t8f)

    12 8-bit Timer (T8F) 12.1 8-bit Timer Overview The S1C17001 incorporates an 8-bit timer with Fine mode. The 8-bit timer consists of an 8-bit presettable down counter and an 8-bit reload data register holding the preset values. The timer counts down from the initial value set in the reload data register and outputs an underflow signal when the counter underflows.

  • Page 135: Bit Timer Count Mode

    The 8-bit timer should be set to this mode to set a specific wait time. Note: Make sure the 8-bit timer count is halted before changing count mode settings. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 136: Count Clock

    (Default: 0x0) Note: • The prescaler must run before the 8-bit timer. • Make sure the 8-bit timer count is halted before changing count clock settings. For detailed information on the prescaler control, see “9 Prescaler (PSC).” EPSON S1C17001 TECHNICAL MANUAL...

  • Page 137

    Count clock (prescaler output clo ck) frequency [Hz] T8F_TR: Reload data (0 to 255) Note: The UART generates a sampling clock that divides the 8-bit timer output into 1/16 divisions. Be careful when setting the transfer rate. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 138

    The 8-bit timer is reset by writing 1 to PRESER bit (D1/T8F_CTL register). The reload data is preset and the coun- ter is initialized. ∗ PRESER: Timer Reset Bit in the 8-bit Timer Control (T8F_CTL) Register (D1/0x4206) EPSON S1C17001 TECHNICAL MANUAL...

  • Page 139

    One-shot mode Count clock PRESER writing PRUN Set by software Reset by hardware Counter Interrupt request Repeat mode Count clock PRESER writing PRUN Set by software Reset by software Counter Interrupt request Figure 12.6.1: Count operation EPSON S1C17001 TECHNICAL MANUAL...

  • Page 140

    {(T8F_TR + 1) × 16 + TFMD} clk_in ÷ 16 T8F_TR = ——— - TFMD - 16 clk_in: Count clock (prescaler output clock) frequency [Hz] T8F_TR: Reload data (0 to 255) bps: Transfer rate (bit/s) TFMD: Fine mode setting (0 to15) EPSON S1C17001 TECHNICAL MANUAL...

  • Page 141: Fine Mode

    Underflow signal (no correction) Underflow signal (with correction) Delay Output clock (no correction) Output clock (with correction) Figure 12.8.1: Delay cycle insertion in Fine mode After the initial resetting, TFMD[3:0] is set to 0x0, preventing insertion of delay cycles. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 142

    For more information on these interrupt control registers and operations when interrupts occur, see “6 Interrupt Controller (ITC).” Interrupt vectors The 8-bit timer interrupt vector numbers and vector addresses are listed below. Vector number: 12 (0x0c) Vector address: 0x8030 EPSON S1C17001 TECHNICAL MANUAL...

  • Page 143

    Timer mode setting and timer RUN/STOP The 8-bit timer registers are described in detail below. These are 16-bit registers. Note: When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 144: X4200: 8-bit Timer Input Clock Select Register (t8f_clk)

    DF[3:0] Prescaler output clock Reserved PCLK-1/128 PCLK-1/16384 PCLK-1/64 PCLK-1/8192 PCLK-1/32 PCLK-1/4096 PCLK-1/16 PCLK-1/2048 PCLK-1/8 PCLK-1/1024 PCLK-1/4 PCLK-1/512 PCLK-1/2 PCLK-1/256 PCLK-1/1 (Default: 0x0) Note: Make sure the 8-bit timer count is halted before changing count clock settings. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 145: X4202: 8-bit Timer Reload Data Register (t8f_tr)

    This means this reload value and the input clock frequency determine the time elapsed from the point at which the timer starts until the underflow occurs (or between underflows). The time determined is used to obtain the desired wait time, the intervals between periodic interrupts, and the programmable serial interface transfer clock. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 146: X4204: 8-bit Timer Counter Data Register (t8f_tc)

    8-bit timer counter data 0x0 to 0xff Register TC7 = MSB (T8F_TC) TC0 = LSB D[15:8] Reserved D[7:0] TC[7:0]: 8-bit Timer Counter Data Reads out the counter data. (Default: 0x0) This register is read-only and cannot be written to. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 147: X4206: 8-bit Timer Control Register (t8f_ctl)

    D: Indicates the insertion of a delay cycle. Count clock Underflow signal (no correction) Underflow signal (with correction) Delay Output clock (no correction) Output clock (with correction) Figure 12.10.1: Delay cycle insertion in Fine mode D[7:5] Reserved EPSON S1C17001 TECHNICAL MANUAL...

  • Page 148

    0 (R/W): Stop (default) The timer starts counting when PRUN is written as 1 and stops when written as 0. When the timer is stopped, the counter data is retained until reset or until the next RUN state. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 149

    12 8-BIT TIMER (T8F) 12.11 Precautions • The prescaler must run before the 8-bit timer. • Set the count clock and count mode only while the 8-bit timer count is stopped. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 150: Pwm & Capture Timer (t16e)

    13 PWM & CAPTURE TIMER (T16E) 13 PWM & Capture Timer (T16E) 13.1 PWM & Capture Timer Overview The S1C17001 incorporates a single-channel PWM & capture timer. Figure 13.1.1 illustrates the PWM & capture timer configuration. PWM & capture timer...

  • Page 151: Pwm & Capture Timer Operating Modes

    The PWM & capture timer increments counts based on the input signal rising edge. The PWM & capture timer does not use the prescaler in this mode. If no other peripheral modules are using the prescaler clock, the prescaler can be stopped to reduce current consumption. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 152: Setting And Resetting Counter Value

    The counter is reset by hardware if the counter matches compare data B after the count starts. The counter can also be set to any desired value by writing data to T16ETC[15:0] (D[15:0]/T16E_TC register). ∗ T16ETC[15:0]: Counter Data in the PWM Timer Counter Data (T16E_TC) Register (D[15:0]/0x5304) EPSON S1C17001 TECHNICAL MANUAL...

  • Page 153: Compare Data Settings

    The counter reset cycle can be calculated as follows: CB + 1 Counter reset interval= ———— [s] clk_in clk_in Counter reset cycle = ———— [Hz] CB + 1 CB: Compare data B (T16E_CB register value) clk_in: Prescaler output clock frequency EPSON S1C17001 TECHNICAL MANUAL...

  • Page 154: Pwm & Capture Timer Run/stop Control

    In either case, counting continues unaffected. For compare B, counting starts from the counter value 0. T16ERUN T16ERST T16E_CA T16E_CB Input clock T16E_TC Reset Compare A Reset and Compare A Reset and interrupt compare B interrupt compare B interrupt interrupt Figure 13.5.1: Basic counter operation timing EPSON S1C17001 TECHNICAL MANUAL...

  • Page 155: Clock Output Control

    Switching the pin function to TOUT output outputs the level set by INITOL and INVOUT. After the timer out- put starts, the output is maintained at this level until changed by the counter value. Table 13.6.1: Initial output level INITOL INVOUT Initial output level High High EPSON S1C17001 TECHNICAL MANUAL...

  • Page 156

    B set in the T16E_CB register (0x5302), the counter is reset and the output pin is returned to the High level. A compare B interrupt factor is also generated at the same time. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 157

    (2) Setting compare data with A > B (A > B x 2 for Fine mode) generates a compare B match signal only. It does not generate a compare A match signal. In this case, the timer output is fixed at Low (High when IN- VOUT = 1). EPSON S1C17001 TECHNICAL MANUAL...

  • Page 158: Pwm & Capture Timer Interrupts

    The interrupt factor should be cleared with the interrupt processing routine by resetting the T16E module CBIF (to 1) rather than the ITC PWM & capture timer interrupt flag. Note: To prevent generating unnecessary interrupts, reset the corresponding CAIF or CBIF before permitting compare A or compare B interrupts from CAIE or CBIE. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 159

    2. Reset the T16E module interrupt flags CAIF and CBIF within the interrupt processing rou- tine after the interrupt occurs (this also resets the ITC interrupt flag). Interrupt vectors The PWM & capture timer interrupt vector numbers and vector addresses are listed below. Vector number: 11 (0x0b) Vector address: 0x802c EPSON S1C17001 TECHNICAL MANUAL...

  • Page 160

    Interrupt occurrence status display/resetting The PWM & capture timer registers are described in detail below. These are 16-bit registers. Note: When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 161: X5300: Pwm Timer Compare Data A Register (t16e_ca)

    The timer output waveform changes at the same time (rising when INVOUT (D4/ T16E_CTL register) = 0 and trailing when INVOUT = 1). These processes do not affect the counter data or the count process. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 162: X5302: Pwm Timer Compare Data B Register (t16e_cb)

    The data set is compared against the counter data, and a compare B interrupt factor is generated if the contents match. The timer output waveform changes at the same time (rising when INVOUT (D4/ T16E_CTL register) = 0 and trailing when INVOUT = 1). The counter is reset to 0. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 163: X5304: Pwm Timer Counter Data Register (t16e_tc)

    Counter Data (16 bits) T16ETC15 = MSB Register T16ETC0 = LSB (T16E_TC) D[15:0] T16ETC[15:0]: Counter Data Counter data can be read out. (Default: 0x0) The counter value can also be set by writing data to this register. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 164: X5306: Pwm Timer Control Register (t16e_ctl)

    Writing 1 to INVOUT generates a TOUT output active Low signal (Off level = High). When INVOUT is 0, an active High signal (Off level = Low) is generated. Writing 1 to this bit also inverts the initial output level set by INITOL (D8). EPSON S1C17001 TECHNICAL MANUAL...

  • Page 165

    The PWM & capture timer starts the count when T16ERUN is written as 1 and stops when written as 0. The counter data is retained when stopped until the subsequent reset or run. Counting can be resumed when switched from Stop to Run from the data retained. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 166: X5308: Pwm Timer Input Clock Select Register (t16e_clk)

    Prescaler output clock Reserved PCLK-1/128 PCLK-1/16384 PCLK-1/64 PCLK-1/8192 PCLK-1/32 PCLK-1/4096 PCLK-1/16 PCLK-1/2048 PCLK-1/8 PCLK-1/1024 PCLK-1/4 PCLK-1/512 PCLK-1/2 PCLK-1/256 PCLK-1/1 (Default: 0x0) Note: Make sure the PWM & capture timer count is halted before changing count clock settings. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 167: X530a: Pwm Timer Interrupt Mask Register (t16e_imsk)

    Setting CAIE to 1 permits compare A interrupt requests to the ITC. Setting it to 0 prohibits interrupts. The ITC PWM & capture timer interrupt enable bits must also be set to permit interrupts in order to generate interrupts. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 168: X530c: Pwm Timer Interrupt Flag Register (t16e_iflg)

    CAIF and CBIF are reset by writing as 1. Note: To prevent generating unnecessary interrupts, reset the corresponding CAIF or CBIF be- fore permitting compare A or compare B interrupts from CAIE (D0/T16E_IMSK) or CBIE (D1/T16E_IMSK). EPSON S1C17001 TECHNICAL MANUAL...

  • Page 169

    A match signal. In this case, the timer output is fixed at Low (High when INVOUT = 1). • To prevent generating unnecessary interrupts, reset the corresponding CAIF (D0/T16E_IFLG register) or CBIF (D1/T16E_IFLG register) before permitting compare A or compare B interrupts from CAIE (D0/T16E_IMSK register) or CBIE (D1/T16E_IMSK register). EPSON S1C17001 TECHNICAL MANUAL...

  • Page 170: Bit Osc1 Timer (t8osc1)

    14 8-BIT OSC1 TIMER (T8OSC1) 14 8-bit OSC1 Timer (T8OSC1) 14.1 8-bit OSC1 Timer Overview The S1C17001 incorporates a single-channel 8-bit OSC1 timer that uses the OSC1 clock as its oscillation source. Figure 14.1.1 illustrates the 8-bit OSC1 timer configuration. 8-bit OSC1 timer...

  • Page 171: Bit Osc1 Timer Count Mode

    The 8-bit OSC1 timer should be set to this mode to set a specific wait time. Note: Make sure the 8-bit OSC1 timer count is halted before changing count mode settings. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 172

    ∗ T8O1CE: T8OSC1 Clock Enable Bit in the T8OSC1 Clock Control (OSC_T8OSC1) Register (D0/0x5065) Note: Make sure the 8-bit OSC1 timer count is halted before changing count clock settings. For detailed information on clock control, refer to “7 Oscillator Circuit (OSC).” EPSON S1C17001 TECHNICAL MANUAL...

  • Page 173: Resetting 8-bit Osc1 Timer

    ∗ T8ORST: Timer Reset Bit in the 8-bit OSC1 Timer Control (T8OSC1_CTL) Register (D4/0x50c0) Normally, the counter should be reset by writing 1 to this bit before starting the count. The counter is reset by hardware if the counter matches compare data after the count starts. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 174

    The compare match cycle can be calculated as follows: CMP + 1 Compare match interval = ————— [s] clk_in clk_in Compare match cycle = ————— [Hz] CMP + 1 CMP: Compare data (T8OSC1_CMP register value) clk_in: 8-bit OSC1 timer count clock frequency EPSON S1C17001 TECHNICAL MANUAL...

  • Page 175: Bit Osc1 Timer Run/stop Control

    T8ORST T8OCMP Input clock T8OCNT Reset Reset & compare match interrupt Repeat mode T8ORUN T8ORST T8OCMP Input clock T8OCNT Reset Reset & Reset & compare match interrupt compare match interrupt Figure 14.6.1: Basic counter operation timing EPSON S1C17001 TECHNICAL MANUAL...

  • Page 176: Bit Osc1 Timer Interrupts

    EIEN4 to 0. EIFT4 is set to 1 by the interrupt signal from the T8OSC1 module regardless of the EIEN4 set- ting (even if it is set to 0). EILV4[2:0] sets the 8-bit OSC1 timer interrupt level (0 to 7). EPSON S1C17001 TECHNICAL MANUAL...

  • Page 177

    2. Reset the 8-bit OSC module interrupt flags T8OIF within the interrupt processing routine after the interrupt occurs (this also resets the ITC interrupt flag). Interrupt vectors The 8-bit OSC timer interrupt vector numbers and vector addresses are listed below. Vector number: 8 (0x08) Vector address: 0x8020 EPSON S1C17001 TECHNICAL MANUAL...

  • Page 178

    Interrupt occurrence status display/resetting The 8-bit OSC1 timer registers are described in detail below. These are 8-bit registers. Note: When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 179: X50c0: 8-bit Osc1 Timer Control Register (t8osc1_ctl)

    0 (R/W): Stop (default) The timer starts counting when T8ORUN is written as 1 and stops when written as 0. When the timer is stopped, the counter data is retained until reset or until the next RUN state. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 180: X50c1: 8-bit Osc1 Timer Counter Data Register (t8osc1_cnt)

    0x0 to 0xff 0xff Timer Counter (8 bits) T8OCNT7 = MSB Data Register T8OCNT0 = LSB (T8OSC1_CNT) D[7:0] T8OCNT[7:0]: Counter Data Reads out the counter data. (Default: 0xff) This register is read-only and cannot be written to. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 181: X50c2: 8-bit Osc1 Timer Compare Data Register (t8osc1_cmp)

    Sets the 8-bit OSC1 timer compare data. (Default: 0x0) The data set is compared against the counter data, and a compare match interrupt factor is generated if the contents match. And the counter is reset to 0. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 182: X50c3: 8-bit Osc1 Timer Interrupt Mask Register (t8osc1_imsk)

    Setting T8OIE to 1 permits 8-bit OSC1 timer interrupt requests to the ITC. Setting it to 0 prohibits in- terrupts. The ITC 8-bit OSC1 timer interrupt enable bits must also be set to permit interrupts in order to generate interrupts. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 183: X50c4: 8-bit Osc1 Timer Interrupt Flag Register (t8osc1_iflg)

    2. Reset the T8OSC1 module interrupt flag T8OIF within the interrupt processing routine after the in- terrupt occurs (this also resets the ITC interrupt flag). T8OIF is reset by writing as 1. Note: To prevent generating unnecessary interrupts, reset T8OIF before permitting compare match interrupts using T8OIE (D0/T8OSC1_IMSK register). EPSON S1C17001 TECHNICAL MANUAL...

  • Page 184

    • Set the count clock and count mode only while the 8-bit OSC1 timer count is stopped. • To prevent generating unnecessary interrupts, reset T8OIF (D0/T8OSC1_IFLG register) before permitting com- pare match interrupts using T8OIE (D0/T8OSC1_IMSK register). EPSON S1C17001 TECHNICAL MANUAL...

  • Page 185

    14 8-BIT OSC1 TIMER (T8OSC1) This page intentionally left blank. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 186: Clock Timer (ct)

    15.1 Clock Timer Overview The S1C17001 incorporates a single-channel clock timer that uses the OSC1 clock as its oscillation source. The clock timer consists of an 8-bit binary counter that uses the 256 Hz signal divided from the OSC1 clock as the input clock and allows data for each bit (128 Hz to 1 Hz) to be read out by software.

  • Page 187: Operation Clock

    The OSC module does not include a 256 Hz clock output control bit. The 256 Hz clock is normally fed to the clock timer when the OSC1 oscillation is on. For detailed information on OSC1 oscillator circuit control, refer to “7 Oscillator Circuit (OSC).” EPSON S1C17001 TECHNICAL MANUAL...

  • Page 188: Clock Timer Resetting

    Reset the clock timer by writing 1 to the CTRST bit (D4/CT_CTL register). This clears the counter to 0. ∗ CTRST: Clock Timer Reset Bit in the Clock Timer Control (CT_CTL) Register (D4/0x5000) Apart from this operation, the counter is also cleared by initial resetting. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 189: Clock Timer Run/stop Control

    “+1.” 1 is retained for CTRUN reading until the timer actually stops. Figure 15.4.2 shows the Run/Stop control timing chart. 256Hz CTRUN(RD) CTRUN(WR) CT_CNT register 0x57 0x58 0x59 0x5a 0x5b 0x5c Figure 15.4.2: Run/Stop control timing chart EPSON S1C17001 TECHNICAL MANUAL...

  • Page 190: Clock Timer Interrupts

    ∗ EILV3[2:0]: CT Interrupt Level Bits in the External Interrupt Level Setup (ITC_ELV1) Register 1 (D[10:8]/0x4308) Interrupt trigger mode selection bit inside ITC (Fix at 1) ∗ EITG3: CT Interrupt Trigger Mode Select Bit in the External Interrupt Level Setup (ITC_ELV1) Register 1 (D12/0x4308) EPSON S1C17001 TECHNICAL MANUAL...

  • Page 191

    2. Reset the CT module interrupt flags CTIF* within the interrupt processing routine after the interrupt occurs (this also resets the ITC interrupt flag). Interrupt vectors The clock timer interrupt vector numbers and vector addresses are listed below. Vector number: 7 (0x07) Vector address: 0x801c EPSON S1C17001 TECHNICAL MANUAL...

  • Page 192

    Interrupt occurrence status display/resetting The clock timer registers are described in detail below. These are 8-bit registers. Note: When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 193: X5000: Clock Timer Control Register (ct_ctl)

    0 (R/W): Stop (default) The clock timer starts counting when CTRUN is written as 1 and stops when written as 0. The counter data is retained at Stop state until a reset or the next Run state. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 194: X5001: Clock Timer Counter Register (ct_cnt)

    Reads out the counter data. (Default: 0xff) This register is read-only and cannot be written to. The bits correspond to various frequencies, as follows: D7: 1Hz D6: 2Hz D5: 4Hz D4: 8Hz D3: 16Hz D2: 32Hz D1: 64Hz D0: 128Hz EPSON S1C17001 TECHNICAL MANUAL...

  • Page 195: X5002: Clock Timer Interrupt Mask Register (ct_imsk)

    Permits or prohibits 2 Hz signal interrupts. 1 (R/W): Interrupt permitted 0 (R/W): Interrupt prohibited (default) CTIE1: 1 Hz Interrupt Enable Bit Permits or prohibits 1 Hz signal interrupts. 1 (R/W): Interrupt permitted 0 (R/W): Interrupt prohibited (default) EPSON S1C17001 TECHNICAL MANUAL...

  • Page 196: X5003: Clock Timer Interrupt Flag Register (ct_iflg)

    Interrupt flag indicating the 1 Hz interrupt factor occurrence status. 1(R): Interrupt factor present 0(R): No interrupt factor (default) 1(W): Reset flag 0(W): Disabled Setting CTIE1 (D0/CT_IMSK register) to 1 sets CTIF1 to 1 at the 1 Hz signal falling edge. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 197

    • Executing the slp command will destabilize a running clock timer (CTRUN = 1) during recovery from SLEEP state. When switching to SLEEP state, set the clock timer to STOP (CTRUN = 0) before executing the slp com- mand. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 198: Stopwatch Timer (swt)

    16.1 Stopwatch Timer Overview The S1C17001 incorporates a 1/100-second and 1/10-second stopwatch timer. The stopwatch timer consists of a 4-bit 2-stage BCD counter (1/100 and 1/10 second) that uses the 256 Hz signal divided from the OSC1 clock as the input clock and allows count data to be read out by software.

  • Page 199: Bcd Counters

    The 1/10-second counter counts the approximate 10 Hz signal generated by the 1/100-second counter at a ratio of 4:6, and generates a 1 Hz signal. Count-up will be pseudo 1/10-second counting at 25/256-second and 26/256-second intervals. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 200

    The OSC module does not include a 256 Hz clock output control bit. The 256 Hz clock is normally fed to the stop- watch timer when the OSC1 oscillation is on. For detailed information on OSC1 oscillator circuit control, refer to “7 Oscillator Circuit (OSC).” EPSON S1C17001 TECHNICAL MANUAL...

  • Page 201: Stopwatch Timer Resetting

    Reset the stopwatch timer by writing 1 to the SWTRST bit (D4/SWT_CTL register). This clears the counter to 0. ∗ SWTRST: Stopwatch Timer Reset Bit in the Stopwatch Timer Control (SWT_CTL) Register (D4/0x5020) Apart from this operation, the counter is also cleared by initial resetting. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 202: Stopwatch Timer Run/stop Control

    Stop state after counting an additional “+1.” 1 is retained for SWTRUN reading until the timer actually stops. Figure 16.5.2 shows the Run/Stop control timing chart. 256Hz SWTRUN(RD) SWTRUN(WR) SWT_BCNT register Figure 16.5.2: Run/Stop control timing chart EPSON S1C17001 TECHNICAL MANUAL...

  • Page 203: Stopwatch Timer Interrupts

    ∗ EILV2[2:0]: SWT Interrupt Level Bits in the External Interrupt Level Setup (ITC_ELV1) Register 1 (D[2:0]/0x4308) Interrupt trigger mode selection bit inside ITC (Fix at 1) ∗ EITG2: SWT Interrupt Trigger Mode Select Bit in the External Interrupt Level Setup (ITC_ELV1) Register 1 (D4/0x4308) EPSON S1C17001 TECHNICAL MANUAL...

  • Page 204

    2. Reset the SWT module interrupt flag SIF* within the interrupt processing routine after the interrupt occurs (this also resets the ITC interrupt flag). Interrupt vectors The stopwatch timer interrupt vector numbers and vector addresses are listed below. Vector number: 6 (0x06) Vector address: 0x8018 EPSON S1C17001 TECHNICAL MANUAL...

  • Page 205

    Interrupt occurrence status display/resetting The stopwatch timer registers are described in detail below. These are 8-bit registers. Note: When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 206: X5020: Stopwatch Timer Control Register (swt_ctl)

    0 (R/W): Stop (default) The stopwatch timer starts counting when SWTRUN is written as 1 and stops when written as 0. The counter data is retained at Stop state until a reset or the next Run state. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 207: X5021: Stopwatch Timer Bcd Counter Register (swt_bcnt)

    Read the 1/10-second counter BCD data. (Default: 0) This register is read-only and cannot be written to. D[3:0] BCD100[3:0]: 1/100 Sec. BCD Counter Value Read the 1/100-second counter BCD data. (Default: 0) This register is read-only and cannot be written to. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 208: X5022: Stopwatch Timer Interrupt Mask Register (swt_imsk)

    Permits or prohibits 10 Hz signal interrupts. 1 (R/W): Interrupt permitted 0 (R/W): Interrupt prohibited (default) SIE100: 100 Hz Interrupt Enable Bit Permits or prohibits 100 Hz signal interrupts. 1 (R/W): Interrupt permitted 0 (R/W): Interrupt prohibited (default) EPSON S1C17001 TECHNICAL MANUAL...

  • Page 209: X5023: Stopwatch Timer Interrupt Flag Register (swt_iflg)

    Interrupt flag indicating the 100 Hz interrupt factor occurrence status. 1(R): Interrupt factor present 0(R): No interrupt factor (default) 1(W): Reset flag 0(W): Disabled Setting SIE100 (D0/SWT_IMSK register) to 1 sets SIF100 to 1 at the 100 Hz signal falling edge. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 210

    • Executing the slp command will destabilize a running stopwatch timer (SWTRUN = 1) during recovery from SLEEP state. When switching to SLEEP state, set the stopwatch timer to STOP (SWTRUN = 0) before executing the slp command. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 211

    16 STOPWATCH TIMER (SWT) This page intentionally left blank. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 212: Watchdog Timer (wdt)

    17 Watchdog Timer (WDT) 17.1 Watchdog Timer Overview The S1C17001 incorporates a watchdog timer that uses the OSC1 oscillator circuit as its oscillation source. The watchdog timer generates an NMI or reset (selectable via software) to the CPU if not reset within 131,072/f...

  • Page 213

    The OSC module does not include a 256 Hz clock output control bit. The 256 Hz clock is normally fed to the watchdog timer when the OSC1 oscillation is on. For detailed information on OSC1 oscillator circuit control, refer to “7 Oscillator Circuit (OSC).” EPSON S1C17001 TECHNICAL MANUAL...

  • Page 214: Watchdog Timer Control

    The clock fed from the OSC module is stopped in SLEEP mode, which also stops the watchdog timer. To pre- vent generation of an unnecessary NMI or Reset after canceling SLEEP mode, reset the watchdog timer before executing the slp command. The watchdog should also be stopped as required using WDTRUN[3:0]. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 215

    Timer mode setting and NMI status display The watchdog timer registers are described in detail below. These are 8-bit registers. Note: When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 216: X5040: Watchdog Timer Control Register (wdt_ctl)

    Controls the watchdog timer Run/Stop. Values other than 0b1010 (R/W): Run 0b1010 (R/W): Stop (default) The watchdog timer must also be reset to prevent generation of an unnecessary NMI or Reset while the watchdog timer operates. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 217: X5041: Watchdog Timer Status Register (wdt_st)

    The WDTST set to 1 is cleared to 0 by resetting the watchdog timer. This is also set by a counter overflow if reset output is selected, but is cleared by initial resetting and cannot be confirmed. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 218

    • When the watchdog timer is running, this must be reset by software within a 131,072 f seconds (4 seconds OSC1 when f = 32.768 kHz) cycle. OSC1 • The watchdog timer must also be reset to prevent generation of an unnecessary NMI or Reset while the watchdog timer operates. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 219

    17 WATCHDOG TIMER (WDT) This page intentionally left blank. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 220: Uart

    18 UART 18.1 UART Configuration The S1C17001 incorporates a single-channel UART. The UART transfers asynchronous data with external devices at a transfer rate of 150 to 460,800 bps (115,200 bps in IrDA mode). It includes a 2-byte receive data buffer and 1-byte transmit data buffer and is capable of full-duplex communications.

  • Page 221: Uart Pin

    P25 → SCLK (only when using external clock) ∗ P25MUX: P25 Port Function Select Bit in the P2 Port Function Select (P2_PMUX) Register (D5/0x52a2) For detailed information on pin function switching, refer to “10.2 Input/output Pin Function Selection (Port MUX).” EPSON S1C17001 TECHNICAL MANUAL...

  • Page 222: Transfer Clock

    Note: • The UART generates a sampling clock that divides the 8-bit timer output into 1/16 divisions. Be careful when setting the transfer rate. • To input the external clock via the SCLK pin, the clock frequency must be less than half of the PCLK and have a duty ratio of 50%. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 223: Transfer Data Settings

    CHLN = 1, PREN = 1, STPB = 0 CHLN = 1, PREN = 0, STPB = 1 CHLN = 1, PREN = 1, STPB = 1 s1: Start bit, s2 & s3: Stop bits, p: Parity bit Figure 18.4.1: Transfer data format EPSON S1C17001 TECHNICAL MANUAL...

  • Page 224: Data Transfer Control

    The TRBS flag indicates the shift register status. This flag switches to 1 when transmission data is loaded from the transmit data buffer to the shift register and reverts to 0 once the data is sent. Read this flag to check wheth- er the transmission circuit is operating or at standby. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 225

    The contents of the receive data buffer must be read out before an overrun error occurs. For detailed information on overrun errors, refer to Section 18.6. The volume of data received can be checked by reading these flags. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 226

    Setting the RXEN bit to 0 empties the transmission and receive data buffers, clearing any remaining data. The data being transferred cannot be guaranteed if RXEN is set to 0 while data is being sent or received. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 227: Receive Errors

    If an overrun error occurs, the overrun error flag OER (D4/UART_ST register) is set to 1. The receiving operation continues even if this error occurs. The OER flag (D4/UART_ST register) is reset to 0 by writing as 1. ∗ OER: Overrun Error Flag in the UART Status (UART_ST) Register (D4/0x4100) EPSON S1C17001 TECHNICAL MANUAL...

  • Page 228: Uart Interrupts

    You can inspect the RDRY and RD2B flags in the UART interrupt processing routine to determine whether the UART interrupt is attributable to a receive buffer full. If RDRY or RD2B is 1, the received data can be read from the receive data buffer by the interrupt processing routine. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 229

    For detailed information on these interrupt registers and operations when interrupts occur, refer to “6 Interrupt Controller (ITC).” Interrupt vectors The UART interrupt vector numbers and vector addresses are as listed below. Vector number: 16 (0x10) Vector address: 0x8040 EPSON S1C17001 TECHNICAL MANUAL...

  • Page 230: Irda Interface

    To use the IrDA interface function, set IRMD (D0/UART_EXP register) to 1. This enables the RZI modulation/ demodulation circuit. ∗ IRMD: IrDA Mode Select Bit in the UART Expansion (UART_EXP) Register (D0/0x4105) Note: This must be set before setting other UART conditions. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 231

    Serial data transfer control Data transfer control in IrDA mode is identical to that for normal interfaces. For detailed information on data format settings and data transfer and interrupt control methods, refer to the previous discussions. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 232

    UART Expansion Register IrDA mode setting The UART registers are described in detail below. These are 8-bit registers. Note: When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 233: X4100: Uart Status Register (uart_st)

    Second byte not received (default) RD2B is set to 1 when the second byte of data is loaded into the receive data buffer and is reset to 0 when the first data is read from the receive data buffer. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 234

    Buffer empty (default) 0 (R): Data exists TDBE is reset to 0 when transmit data is written to the transmit data buffer and is set to 1 when the data is transferred to the shift register. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 235: X4101: Uart Transmit Data Register (uart_txd)

    TXD7 (MSB) is invalid in 7-bit mode. Serial converted data is output from the SOUT pin, with the LSB first bits set to 1 as High level and bits set to 0 as Low level. This register can also be read from. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 236: X4102: Uart Receive Data Register (uart_rxd)

    Serial data input via the SIN pin is converted to parallel, with the initial bit as LSB, the High level bit as 1, and the Low level bit as 0. This data is then loaded into the receive data buffer. This register is read-only. (Default: 0x0) EPSON S1C17001 TECHNICAL MANUAL...

  • Page 237: X4103: Uart Mode Register (uart_mod)

    0 (R/W): Internal clock (default) Selects whether the internal clock (8-bit timer output clock) or external clock (input via SCLK pin) is used. Writing 1 to SSCK selects the external clock; Writing 0 to it selects the internal clock. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 238: X4104: Uart Control Register (uart_ctl)

    Set RXEN to 1 before starting UART transfers. Setting RXEN to 0 will stop data transfers. Set the transfer conditions while RXEN is 0. Preventing transfers by writing 0 to RXEN also clears transfer data buffers. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 239: X4105: Uart Expansion Register (uart_exp)

    Switches the IrDA interface function on and off. 1 (R/W): On 0 (R/W): Off (default) Set this to 1 to use the IrDA interface. When this bit is set to 0, this module functions as a normal UART, with no IrDA functions. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 240

    • The IrDA interface demodulation circuit treats Low pulses with a width of at least 2 IrDA receive detection clock cycles as valid. Select the appropriate prescaler output clock to enable detection of input pulses with a minimum width of 1.41 μs as a 2 IrDA receive detection clock. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 241

    18 UART This page intentionally left blank. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 242: Spi Configuration

    19 SPI 19.1 SPI Configuration The S1C17001 incorporates a synchronized serial interface module (SPI). This SPI module supports both Master and Slave modes and is used for 8-bit data transfers. Four different data transfer timing patterns (clock phase and polarity) can be selected.

  • Page 243: Spi Input/output Pins

    ∗ P22MUX: P22 Port Function Select Bit in the P2 Port Function Select (P2_PMUX) Register (D2/0x52a2) P17 → #SPISS ∗ P17MUX: P17 Port Function Select Bit in the P1 Port Function Select (P1_PMUX) Register (D7/0x52a1) For detailed information on pin function switching, refer to “10.2 Input/Output Pin Function Selection (Port MUX).” EPSON S1C17001 TECHNICAL MANUAL...

  • Page 244: Spi Clock

    Note: The frequency of the clock input via the SPICLK pin must be less than 1/3 of the PCLK and have a clock duty ratio of 50%. PCLK SPICLK input SPICLK differentiated signal SPI clock (internal use) Figure 19.3.2: Slave mode SPI clock EPSON S1C17001 TECHNICAL MANUAL...

  • Page 245: Data Transfer Condition Settings

    SPICLK(CPOL = 1, CPHA = 0) SPICLK(CPOL = 0, CPHA = 1) SPICLK(CPOL = 0, CPHA = 0) SDI/SDO D7 (MSB) D0 (LSB) Receive data load timing to shift register Figure 19.4.1: Clock and data transfer timing EPSON S1C17001 TECHNICAL MANUAL...

  • Page 246

    The Slave mode SPBSY flag indicates the SPI slave selection signal (#SPISS pin) status. The flag has the value 1 when the SPI module is selected in Slave mode and the value 0 when the module is not selected. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 247

    In Master mode, the SPBSY flag indicating the shift register state can be used in the same way while transfer- ring data. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 248

    Setting the SPEN bit to 0 empties the transmission and receive data buffers, clearing any remaining data. The data being transferred cannot be guaranteed if SPEN is set to 0 while data is being sent or received. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 249: Spi Interrupts

    If the IIEN6 interrupt enable bit is set to 1, the ITC sends an interrupt request to the S1C17 core. To prohibit SPI interrupts, set IIEN6 to 0. The IIFT6 flag is set to 1 by a SPI interrupt request pulse, regardless of the IIEN6 bit setting (i.e., even if set to 0). EPSON S1C17001 TECHNICAL MANUAL...

  • Page 250

    For detailed information on these interrupt registers and operations when interrupts occur, refer to “6 Interrupt Controller (ITC).” Interrupt vectors The SPI interrupt vector numbers and vector addresses are as listed below. Vector number: 18 (0x12) Vector address: 0x8040 EPSON S1C17001 TECHNICAL MANUAL...

  • Page 251

    Note: • When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1. • Always use 16-bit access commands to read and write to/from the SPI register. 32-bit and 8-bit access commands cannot be used to read and write to/from the SPI register. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 252: X4320: Spi Status Register (spi_st)

    SPTBE is set to 0 when transmit data is written to the SPI_TXD register (transmit data buffer, 0x4322), and is set to 1 when the data is transferred to the shift register (when transmission starts). Transmission data is written to the SPI_TXD register when this bit is 1. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 253: X4322: Spi Transmit Data Register (spi_txd)

    Serial converted data is output from the SDO pin with MSB leading, with the bit set to 1 as High level and the bit set to 0 as Low level. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 254: X4324: Spi Receive Data Register (spi_rxd)

    Serial data input from the SDI pin with MSB leading is converted to parallel, with the High level bit set to 1 and the Low level bit set to 0. The data is the loaded into this register. This register is read-only. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 255: X4326: Spi Control Register (spi_ctl)

    SPICLK(CPOL = 1, CPHA = 0) SPICLK(CPOL = 0, CPHA = 1) SPICLK(CPOL = 0, CPHA = 0) SDI/SDO D7 (MSB) D0 (LSB) Receive data load timing to shift register Figure 19.7.1: Clock and data transfer timing EPSON S1C17001 TECHNICAL MANUAL...

  • Page 256

    Setting SPEN to 1 starts the SPI module operation, enabling data transfer. Setting SPEN to 0 stops the SPI module operation. Note: The SPEN bit should be set to 0 before setting the CPHA, CPOL, and MSSL bits. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 257

    8-bit access commands cannot be used to read and write to/from the SPI register. • Do not access the SPI_CTL register (0x4326) while the SPBSY flag (D2/SPI_ST register) is set to 1 (while data is being transferred). ∗ SPBSY: Transfer Busy Flag in the SPI Status (SPI_ST) Register (D2/0x4320) EPSON S1C17001 TECHNICAL MANUAL...

  • Page 258

    20.1 I C Configuration The S1C17001 incorporates an I C bus interface module for high-speed synchronized serial communications. The C module operates as a master device (as single master only) using the clock fed from the 16-bit timer Ch.2. It supports standard (100 kbps) and fast (400 kbps) modes as well as 7-bit/10-bit slave address mode.

  • Page 259

    ∗ P14MUX: P14 Port Function Select Bit in the P1 Port Function Select (P1_PMUX) Register (D4/0x52a1) P15 → SCL ∗ P15MUX: P15 Port Function Select Bit in the P1 Port Function Select (P1_PMUX) Register (D5/0x52a1) For detailed information on pin function switching, refer to “10.2 Input/Output Pin Function Selection (Port MUX).” EPSON S1C17001 TECHNICAL MANUAL...

  • Page 260

    “11 16-bit Timer (T16).” The I C module does not function as a slave device. The SCL input pin is used to check the I C bus SCL signal sta- tus. It is not used for synchronization clock input. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 261: Settings Before Data Transfer

    Note that using this function requires setting the I C clock (16-bit timer Ch.2 output clock) frequency to 1/6 or less of PCLK. ∗ NSERM: Noise Remove On/Off Bit in the I C Control (I2C_CTL) Register (D4/0x4342) EPSON S1C17001 TECHNICAL MANUAL...

  • Page 262

    Transfer direction Slave address 0: Master → Slave (data transmission) first 2 bits 1: Slave → Master (date receipt) Second data sent Slave address last 8 bits Figure 20.5.2: Slave address and transmission data specifying transfer direction EPSON S1C17001 TECHNICAL MANUAL...

  • Page 263

    C module is currently transmitting or at standby. The RTACK bit indicates whether or not the slave device returned an ACK for the previous transmission. RTACK is 0 if an ACK was returned and 1 if ACK was not returned. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 264

    STP will be disabled if any of TXE, RXE, or STRT is 1. The I C module does not support repeated start condition. The stop condition cannot be omitted before generat- ing the start condition for the subsequent data transfer. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 265

    SDA (output) STRT TBUSY RBUSY RBRDY RTACK (ACK receipt) (ACK receipt) Shift register shift valid shift shift shift shift shift shift shift RTDT[7:0] D[7:0] Interrupt Figure 20.5.6: I C timing chart 2 (Data transmission à Stop condition) EPSON S1C17001 TECHNICAL MANUAL...

  • Page 266

    Cleared by reading RTDT[7:0] RBUSY RBRDY RTACK (ACK transmission) (ACK transmission) Shift register shift valid shift shift shift shift shift shift shift valid RTDT[7:0] D[7:0] D[7:0] Interrupt C timing chart 4 (Data receipt ➔ Stop condition) Figure 20.5.8: I EPSON S1C17001 TECHNICAL MANUAL...

  • Page 267

    STP = 0 TXE = 0 RXE = 0 TBUSY RBUSY RBRDY RTACK (ACK receipt) Shift register valid shift shift shift valid shift shift RTDT[7:0] A[6:0] + DIR D[7:0] Interrupt Figure 20.5.9: I C timing chart 5 (Wait) EPSON S1C17001 TECHNICAL MANUAL...

  • Page 268: I 2 C Interrupts

    The IIFT7 flag is set to 1 by a I C interrupt request pulse, regardless of the IIEN7 bit setting (i.e., even if set to 0). The IILV7[2:0] interrupt level setting bit sets the I C interrupt level (0 to 7). EPSON S1C17001 TECHNICAL MANUAL...

  • Page 269

    For detailed information on these interrupt registers and operations when interrupts occur, refer to “6 Interrupt Controller (ITC).” Interrupt vectors The I C interrupt vector numbers and vector addresses are as listed below. Vector number: 19 (0x13) Vector address: 0x804c EPSON S1C17001 TECHNICAL MANUAL...

  • Page 270

    Note: • When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1. • Always use 16-bit access commands to read and write to/from the I C register. 32-bit and 8-bit access commands cannot be used to read and write to/from the I C register. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 271

    Permits or prohibits I C module operation. 1 (R/W): Permitted 0 (R/W): Prohibited (default) Setting I2CEN to 1 starts the I C module operation, enabling data transfer. Setting I2CEN to 0 stops the I C module operation. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 272

    (D10/I2C_DAT register), and STRT (D0) are set to 0 when data transfer is complete (including ACK transfer). STP is disabled if any of TXE, RXE, or STRT is 1. STP is automatically reset to 0 if the stop condition is generated. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 273

    I C bus SCL line at High. The I C bus subsequently becomes busy. Set STRT to 1 when data transfer starts. STRT is automatically reset to 0 once the start condition is generated. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 274

    0 (R/W): ACK (default) To return an ACK after data has been received, RTACK should be set to 0 before the I C module sends the response bit. To return an NACK, set RTACK to 1. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 275

    Serial data input from the SDA pin with MSB leading is converted to parallel, with the High level bit set to 1 and the Low level bit set to 0, then loaded to this register. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 276

    C interrupt requests to the ITC due to a transmit buffer empty. These interrupt requests are generated when the data written to RTDT[7:0] (D[7:0]/I2C_DAT register) is transferred to the shift register. C interrupts are not generated by transmit buffer empty if TINTE is set to 0. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 277

    20 I This page intentionally left blank. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 278: Remote Controller (remc)

    21 Remote Controller (REMC) 21.1 REMC Configuration The S1C17001 incorporates a remote controller (REMC) module for generating infrared remote control commu- nication signals. The REMC module consists of a carrier generation circuit for generating a carrier signal using the prescaler output clock, an 8-bit down-counter for counting the transferred data length, a modulation circuit for generating transmission data of the specified carrier length, and an edge detection circuit for detecting input signal rising and falling edges.

  • Page 279: Remc Input/output Pin

    ∗ P04MUX: P04 Port Function Select Bit in the P0 Port Function Select (P0_PMUX) Register (D4/0x52a0) P05 → REMO ∗ P05MUX: P05 Port Function Select Bit in the P0 Port Function Select (P0_PMUX) Register (D5/0x52a0) For detailed information on pin function switching, refer to “10.2 Input/output Pin Function Selection (Port MUX).” EPSON S1C17001 TECHNICAL MANUAL...

  • Page 280: Carrier Generation

    The carrier signal is generated from these settings as shown in Figure 21.3.1. Example: CGCLK[3:0] = 0x2 (PCLK-1/4), REMCH[5:0] = 2, REMCL[5:0] = 1 PCLK PSC output clock Count Carrier Carrier H section length Carrier L section length Figure 21.3.1: Carrier signal generation EPSON S1C17001 TECHNICAL MANUAL...

  • Page 281: Data Length Counter Clock Settings

    PCLK-1/16 PCLK-1/2048 PCLK-1/8 PCLK-1/1024 PCLK-1/4 PCLK-1/512 PCLK-1/2 PCLK-1/256 PCLK-1/1 (Default: 0x0) The data length counter can count up to 256. The count clock should be selected to ensure that the data length fits within this range. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 282

    Set the value corresponding to the data pulse length (High or Low section) at the start of transmission to REM- LEN[7:0] (D[7:0]/REMC_LCNT register) to set to the data length counter. ∗ REMLEN[7:0]: Transmit/Receive Data Length Count Bits in the REMC Length Counter (REMC_LCNT) Register (D[7:0]/0x5345) EPSON S1C17001 TECHNICAL MANUAL...

  • Page 283

    Note that if the signal level after the input has changed is not detected for at least two continuous sampling clock cycles, the interrupt factor is interpreted as noise, and no rising or falling edge interrupt is generated. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 284

    Data length counter underflow interrupts are gener- ated even when receiving data and should be used for end/error processing. (4) Data receipt end To end data receipt, write 0 to REMEN after the final data has been received. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 285: Remc Interrupts

    REMC interrupt is attributable to input signal rising edge. The interrupt factor should be cleared as part of the interrupt processing routine by resetting both the ITC REMC interrupt flag and REMC module REMRIF (i.e., setting both to 1). EPSON S1C17001 TECHNICAL MANUAL...

  • Page 286

    For detailed information on these interrupt registers and operations when interrupts occur, refer to “6 Interrupt Controller (ITC).” Interrupt vectors The REMC interrupt vector numbers and vector addresses are as listed below. Vector number: 17 (0x11) Vector address: 0x8040 EPSON S1C17001 TECHNICAL MANUAL...

  • Page 287

    Interrupt occurrence status display and resetting The REMC registers are described in detail below. These are 8-bit registers. Note: When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 288: X5340: Remc Configuration Register (remc_cfg)

    Permits or prohibit data transfer by the REMC module 1 (R/W): Permitted 0 (R/W): Prohibited (default) Setting REMEN to 1 begins transmission or receiving in accordance with REMMD (D1) settings. Setting REMEN to 0 halts REMC module operations. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 289: X5341: Remc Prescaler Clock Select Register (remc_psc)

    Prescaler output clock Reserved PCLK-1/128 PCLK-1/16384 PCLK-1/64 PCLK-1/8192 PCLK-1/32 PCLK-1/4096 PCLK-1/16 PCLK-1/2048 PCLK-1/8 PCLK-1/1024 PCLK-1/4 PCLK-1/512 PCLK-1/2 PCLK-1/256 PCLK-1/1 (Default: 0x0) Note: The clock should be set only while the REMC module is stopped (REMEN/REMC_CFG register = 0). EPSON S1C17001 TECHNICAL MANUAL...

  • Page 290: X5342: Remc H Carrier Length Setup Register (remc_carh)

    The carrier signal is generated from these settings as shown in Figure 21.7.1. Example: CGCLK[3:0] = 0x2 (PCLK-1/4), REMCH[5:0] = 2, REMCL[5:0] = 1 PCLK PSC output clock Count Carrier Carrier H section length Carrier L section length Figure 21.7.1: Carrier signal generation EPSON S1C17001 TECHNICAL MANUAL...

  • Page 291: X5343: Remc L Carrier Length Setup Register (remc_carl)

    Carrier L section length = —————— [s] clk_in REMCH: REMCL[5:0] settings clk_in: Prescaler output clock frequency The H section length is specified by REMCH[5:0] (D[5:0]/REMC_CARH register). The carrier signal is generated from these settings as shown in Figure 21.7.1. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 292: X5344: Remc Status Register (remc_st)

    If REMEN (D0/REMC_CFG register) is set to 1, the REMDT setting is modulated by the carrier signal for data transmission and output from the REMO pin. For data receiving, this bit is set to the value cor- responding to the signal level of the data pulse input. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 293: X5345: Remc Length Counter Register (remc_lcnt)

    0xff using the in- terrupt when the input changes and reading out the count value when the next interrupt occurs due to an input change. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 294: X5346: Remc Interrupt Mask Register (remc_imsk)

    Permits or blocks input signal rising edge interrupts. 1 (R/W): Interrupt permitted 0 (R/W): Interrupt prohibited (default) REMUIE: Underflow Interrupt Enable Bit Permits or blocks data length counter underflow interrupts. 1 (R/W): Interrupt permitted 0 (R/W): Interrupt prohibited (default) EPSON S1C17001 TECHNICAL MANUAL...

  • Page 295: X5347: Remc Interrupt Flag Register (remc_iflg)

    Interrupt flag indicating the underflow interrupt factor occurrence status. 1(R): Interrupt factor present 0(R): No interrupt factor (default) 1(W): Reset flag 0(W): Disabled Setting REMUIE (D1/REMC_IMSK register) to 1 sets REMUIF to 1 when a data length counter under- flow occurs. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 296

    21 REMOTE CONTROLLER (REMC) 21.8 Precautions The prescaler must run before operating the REMC module. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 297

    21 REMOTE CONTROLLER (REMC) This page intentionally left blank. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 298: On-chip Debugger (dbg)

    22.1 Resource Requirements and Debugging Tool Debugging work area Debugging requires a 64-byte debugging work area. In the S1C17001, RAM addresses 0x0007c0 to 0x0007ff are assigned as the debugging work area. When using the debugging function, avoid using this area for any other user applications.

  • Page 299: Debug Break Operation Status

    ∗ O1DBG: OSC1 Peripheral Control (in Debug Mode) Bit in the OSC1 Peripheral Control (MISC_OSC1) Register (D0/0x5322) The 8-bit OSC1 timer does not stop in debug mode, even if O1DBG is set to 1. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 300

    Debug RAM base address display The debug registers are described in detail below. These are 8-bit registers. Note: When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 301: X5322: Osc1 Peripheral Control Register (misc_osc1)

    OSC1 peripheral circuit refers to the following peripheral circuits that operate using the OSC1 clock. • Clock timer • Watchdog timer • Stopwatch timer The 8-bit OSC1 timer does not stop in debug mode, even if O1DBG is set to 1. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 302: Xffff90: Debug Ram Base Register (dbram)

    (32 bits) D23–0 DBRAM[23:0] Debug RAM base address 0x7c0 0x7c0 (DBRAM) D[31:24] Not used (Fixed at 0) D[23:0] DBRAM[23:0]: Debug RAM Base Address Bits Read-only register containing the initial address of the debugging work area (64 bytes). EPSON S1C17001 TECHNICAL MANUAL...

  • Page 303

    22 ON-CHIP DEBUGGER (DBG) This page intentionally left blank. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 304: Basic External Connection Diagram

    DSIO (P33) DCLK (P31) ICD or DST2 (P32) Recommended values for external components Symbol Name Recommended value X'tal1 Crystal oscillator 32.768kHz (MC-146, Epson Toyocom) Gate capacitor Drain capacitor Feedback resistor 10MΩ Drain resistor 0Ω X'tal3 Crystal oscillator 8MHz (CA-301, Epson Toyocom) Ceramic oscillator 0.2~8MHz...

  • Page 305

    DSIO (P33) ICD or DCLK (P31) DST2 (P32) Recommended values for external components Symbol Name Recommended value X'tal1 Crystal oscillator 32.768kHz (MC-146, Epson Toyocom) Gate capacitor Drain capacitor Feedback resistor 10MΩ Drain resistor 0Ω X'tal3 Crystal oscillator 8MHz (CA-301, Epson Toyocom) Ceramic oscillator 0.2~8MHz...

  • Page 306: Electrical Characteristics

    ∗1: With N channel as open drain (Up to 3.9 V permissible for input buffer) Do not apply voltages exceeding this value to fail-safe cell for H level output from external sources. ∗2: Recommended ambient temperature assuming Tj = -40°C to 125°C. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 307: Dc Characteristics

    = 1.65 to 2.7V, V = 0V, Ta = -40 to 85°C Item Code Condition Min. Typ. Max. Units High level input current TEST0, OSC1, OSC3 0.9LV Low level input current TEST0, OSC1, OSC3 0.1LV Input pull-down resistance TEST0 kΩ EPSON S1C17001 TECHNICAL MANUAL...

  • Page 308: Consumption Current

    FLCYC = 4 (1 cycle) ∗1: Current consumption during execution is the value exhibited when operating continuously while fetching the fol- lowing test program from ROM: ALU commands 60.5%, branching commands 17%, memory reading 12%, and memory writing 10.5%. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 309: Ac Characteristics

    = 0V, Ta = -40 to 85°C Item Code Min. Typ. Max. Units SCL cycle time 2500 Start condition hold time Data output delay time Stop condition hold time ∗ f : System operation clock frequency EPSON S1C17001 TECHNICAL MANUAL...

  • Page 310: External Clock Input Ac Characteristics

    24.5.4 System AC Characteristics #RESET Unless otherwise specified: HV = 1.65 to 3.6V, LV = 1.65 to 2.7V, V = 0V, Ta = -40 to 85°C Item Code Min. Typ. Max. Units Reset Low pulse width μs EPSON S1C17001 TECHNICAL MANUAL...

  • Page 311: Oscillation Characteristics

    Note: Use a crystal fundamental wave oscillator for the OSC3 crystal oscillator circuit. Unless otherwise specified: HV = 1.65 to 3.6V, LV = 1.65 to 2.7V, V = 0V, Ta = 25°C Item Code Condition Min. Typ. Max. Units Oscillation start time EPSON S1C17001 TECHNICAL MANUAL...

  • Page 312

    3.224 3.024 3.124 3.224 – – 0.78 – 0.23 – – 0.49 – – 0.40 – – 0.40 – 0.23 0.26 0.29 – – 0.08 – – 0.05 – 0.362 – – 0.362 – A1 Corner EPSON S1C17001 TECHNICAL MANUAL...

  • Page 313

    25 PACKAGE This page intentionally left blank. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 314: Appendix A I/o Register List

    C module enable (16-bit device) 0x4342 I2C_CTL C Control Register C control and transfer status display 0x4344 I2C_DAT C Data Register Transfer data 0x4346 I2C_ICTL C Interrupt Control Register C interrupt control 0x4348 to 0x435f – – Reserved EPSON S1C17001 TECHNICAL MANUAL...

  • Page 315

    P1 Port Function Select Register P1 port function selection 0x52a2 P2_PMUX P2 Port Function Select Register P2 port function selection 0x52a3 P3_PMUX P3 Port Function Select Register P3 port function selection 0x52a4 to 0x52bf – – Reserved EPSON S1C17001 TECHNICAL MANUAL...

  • Page 316

    REMC Interrupt Flag Register Interrupt occurrence status display/reset 0x5348 to 0x535f – – Reserved Note: Addresses marked as “Reserved” or unused peripheral circuit areas not marked in the table must not be accessed by application programs. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 317

    Prescaler Con- 0x4020 D7–2 – reserved – – – 0 when being read. trol Register (8 bits) PRUND Prescaler run/stop in debug mode 1 Run 0 Stop (PSC_CTL) PRUN Prescaler run/stop control 1 Run 0 Stop EPSON S1C17001 TECHNICAL MANUAL...

  • Page 318

    D6–4 IRCLK[2:0] IrDA receive detection clock IRCLK[2:0] Clock 0x0 R/W Register select PCLK-1/128 (UART_EXP) PCLK-1/64 PCLK-1/32 PCLK-1/16 PCLK-1/8 PCLK-1/4 PCLK-1/2 PCLK-1/1 D3–1 – reserved – – – 0 when being read. IRMD IrDA mode select 1 On 0 Off EPSON S1C17001 TECHNICAL MANUAL...

  • Page 319

    0 when being read. TRMD Count mode select 1 One shot 0 Repeat D3–2 – reserved – – – 0 when being read. PRESER Timer reset 1 Reset 0 Ignored PRUN Timer run/stop control 1 Run 0 Stop EPSON S1C17001 TECHNICAL MANUAL...

  • Page 320

    0 when being read. TRMD Count mode select 1 One shot 0 Repeat D3–2 – reserved – – – 0 when being read. PRESER Timer reset 1 Reset 0 Ignored PRUN Timer run/stop control 1 Run 0 Stop EPSON S1C17001 TECHNICAL MANUAL...

  • Page 321

    0 when being read. TRMD Count mode select 1 One shot 0 Repeat D3–2 – reserved – – – 0 when being read. PRESER Timer reset 1 Reset 0 Ignored PRUN Timer run/stop control 1 Run 0 Stop EPSON S1C17001 TECHNICAL MANUAL...

  • Page 322

    D10–8 IILV3[2:0] T16 Ch.2 interrupt level 0 to 7 0x0 R/W Setup Register 1 D7–3 – reserved – – – 0 when being read. (ITC_ILV1) D2–0 IILV2[2:0] T16 Ch.1 interrupt level 0 to 7 0x0 R/W EPSON S1C17001 TECHNICAL MANUAL...

  • Page 323

    (16 bits) D10–8 IILV7[2:0] C interrupt level 0 to 7 0x0 R/W Setup Register 3 D7–3 – reserved – – – 0 when being read. (ITC_ILV3) D2–0 IILV6[2:0] SPI interrupt level 0 to 7 0x0 R/W EPSON S1C17001 TECHNICAL MANUAL...

  • Page 324

    R/W These bits must be set before setting CPOL Clock polarity select 1 Active L 0 Active H SPEN to 1. MSSL Master/slave mode select 1 Master 0 Slave SPEN SPI enable 1 Enable 0 Disable EPSON S1C17001 TECHNICAL MANUAL...

  • Page 325

    RTDT0 = LSB C Interrupt 0x4346 D15–2 – reserved – – – 0 when being read. Control Register (16 bits) RINTE Receive interrupt enable 1 Enable 0 Disable (I2C_ICTL) TINTE Transmit interrupt enable 1 Enable 0 Disable EPSON S1C17001 TECHNICAL MANUAL...

  • Page 326

    32 Hz interrupt flag 1 Cause of 0 Cause of R/W Reset by writing 1. Register interrupt interrupt not CTIF8 8 Hz interrupt flag (CT_IFLG) occurred occurred CTIF2 2 Hz interrupt flag CTIF1 1 Hz interrupt flag EPSON S1C17001 TECHNICAL MANUAL...

  • Page 327

    (8 bits) SIF1 1 Hz interrupt flag 1 Cause of 0 Cause of R/W Reset by writing 1. Flag Register interrupt interrupt not SIF10 10 Hz interrupt flag (SWT_IFLG) occurred occurred SIF100 100 Hz interrupt flag EPSON S1C17001 TECHNICAL MANUAL...

  • Page 328

    Stop Watchdog 0x5041 D7–2 – reserved – – – 0 when being read. Timer Status (8 bits) Register WDTMD NMI/Reset mode select 1 Reset 0 NMI (WDT_ST) WDTST NMI status 1 NMI occurred 0 Not occurred EPSON S1C17001 TECHNICAL MANUAL...

  • Page 329

    0 when being read. Control Register (8 bits) D3–1 T8O1CK[2:0] T8OSC1 clock division ratio select T8O1CK[2:0] Division ratio 0x0 R/W (OSC_T8OSC1) 0x7–0x6 reserved OSC1-1/32 OSC1-1/16 OSC1-1/8 OSC1-1/4 OSC1-1/2 OSC1-1/1 T8O1CE T8OSC1 clock output enable 1 Enable 0 Disable EPSON S1C17001 TECHNICAL MANUAL...

  • Page 330

    Enable Not allowed Not allowed Disable CCLK Control 0x5081 D7–2 – reserved – – – 0 when being read. Register (8 bits) D1–0 CCLK- CCLK clock gear ratio select CCLKGR[1:0] Gear ratio 0x0 R/W (CLG_CCLK) GR[1:0] EPSON S1C17001 TECHNICAL MANUAL...

  • Page 331

    – – – 0 when being read. Timer Interrupt (8 bits) T8OIF 8-bit OSC1 timer interrupt flag 1 Cause of 0 Cause of R/W Reset by writing 1. Flag Register interrupt interrupt not (T8OSC1_IFLG) occurred occurred EPSON S1C17001 TECHNICAL MANUAL...

  • Page 332

    P1[7:0] port interrupt enable 1 Enable 0 Disable Interrupt Mask (8 bits) Register (P1_IMSK) P1 Port 0x5216 D7–0 P1EDGE[7:0] P1[7:0] port interrupt edge select 1 Falling edge 0 Rising edge Interrupt Edge (8 bits) Select Register (P1_EDGE) EPSON S1C17001 TECHNICAL MANUAL...

  • Page 333

    P33 port function select 1 P33 0 DSIO Register P32MUX P32 port function select 1 P32 0 DST2 (P3_PMUX) P31MUX P31 port function select 1 P31 0 DCLK P30MUX P30 port function select 1 FOUT3 0 P30 EPSON S1C17001 TECHNICAL MANUAL...

  • Page 334

    0 when being read. R/W Reset by writing 1. Interrupt (16 bits) CBIF Compare B interrupt flag 1 Cause of 0 Cause of Flag Register interrupt interrupt not CAIF Compare A interrupt flag (T16E_IFLG) occurred occurred EPSON S1C17001 TECHNICAL MANUAL...

  • Page 335

    5 cycles 4 cycles 3 cycles 2 cycles OSC1 Peripheral 0x5322 D7–1 – reserved – – – 0 when being read. Control Register (8 bits) O1DBG OSC1 peripheral control in debug 1 Run 0 Stop (MISC_OSC1) mode EPSON S1C17001 TECHNICAL MANUAL...

  • Page 336

    0 when being read. Flag Register (8 bits) REMFIF Falling edge interrupt flag 1 Cause of 0 Cause of R/W Reset by writing 1. (REMC_IFLG) interrupt interrupt not REMRIF Rising edge interrupt flag occurred occurred REMUIF Underflow interrupt flag EPSON S1C17001 TECHNICAL MANUAL...

  • Page 337

    0xffff84 D7–0 IDIR[7:0] Processor ID 0x10 0x10 Register (8 bits) 0x10: S1C17 Core (IDIR) Debug RAM 0xffff90 D31–24 – Unused (fixed at 0) Base Register (32 bits) D23–0 DBRAM[23:0] Debug RAM base address 0x7c0 0x7c0 (DBRAM) EPSON S1C17001 TECHNICAL MANUAL...

  • Page 338: Appendix B Power Saving

    Current consumption will vary dramatically, depending on CPU operating mode, operation clock frequency, and the peripheral circuits being operated. Listed below are the control methods for saving power. B.1 Clock Control Power Saving Figure B.1.1 illustrates the S1C17001 clock system. SLEEP, On/Off control Clock source...

  • Page 339

    • 8-bit timer • 16-bit timer Ch.0 to Ch.2 • Interrupt controller • SPI • I • P port and port MUX (control register, chattering filter) • PWM & capture timer • MISC register • Remote controller EPSON S1C17001 TECHNICAL MANUAL...

  • Page 340

    Started by PCLK peripheral circuit interrupt factors permitted by the interrupt controller. If the CPU IE flag is 0, the CPU executes commands following the halt command, rejecting the interrupt. If the IE flag is 1, the CPU branches to an interrupt processing routine. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 341: Appendix C Mounting Precautions

    Account for resistance fluctuations when setting the #RESET pin pull-up resistance for constants settings. • Components such as capacitors and resistors connected to the #RESET pin should have the shortest connec- tions possible to prevent noise-induced resets. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 342

    The highest risk of noise occurs in configurations in which a line is sandwiched between multiple signal lines that vary in synchrony. You can minimize noise effects by reducing the length of parallel sections (limit to a few cm) or by increasing the separation (to at least 2 mm). EPSON S1C17001 TECHNICAL MANUAL...

  • Page 343

    (testing) processes; (2) electromagnetically-induced noise generated by solder irons during soldering. In particular, the soldering iron GND (tip potential) must be at the same potential as the IC GND during solder- ing. EPSON S1C17001 TECHNICAL MANUAL...

  • Page 344: Appendix D Initialization Routine

    Xld.a %sp, 0x7c0 ; ----- Memory controller ---------------- Xld.a %r1, 0x5320 ; MISC register base address ; ROM Xld.a %r0, 0x04 ; 1 cycle access . . . (5) ld.b [%r1], %r0 ; [0x5320] <= 0x04 EPSON S1C17001 TECHNICAL MANUAL...

  • Page 345

    (See “3 Memory Map and Bus Control.”) (6) Sets interrupt trigger mode to level trigger for the following peripheral circuits. P0 port, P1 port, stopwatch timer, clock timer, 8-bit OSC1 timer, PWM & capture timer (See “6 Interrupt Controller (ITC).”) EPSON S1C17001 TECHNICAL MANUAL...

  • Page 346: Appendix E S1c17001 Mask Rom Code Development

    Code Development (1) The S1C17001 mask ROM code was developed using the S1C17704 Flash microprocessor. (2) ROM data is provided to Epson in “file.PAn” (winmdc output) format. Final user verification of ROM data should use “file.psa” (sconv32 output) format. (3) Set the following arguments when executing moto2ff in the S1C17001.

  • Page 347: Appendix F Revision History

    APPENDIX F REVISION HISTORY Appendix F: Revision History Rev. No. Date Page Section Details 2007.9.21 1.3.1 Pinout Diagram Figure 1.3.1.1 changed 1.3.2 Pin Descriptions Table 1.3.2.1 changed 23-1 23 Basic External Connection Diagram Figure changed and added Sample program changed AP-31 Appendix D: Initialization Routine 2007.10.28...

  • Page 348

    APPENDIX F REVISION HISTORY Rev. No. Date Page Section Details Description changed 2007.10.28 13-8 13.6 Clock Output Control “If the counter data register … A bit 0 (T16ECA0) value.” ------ “Precautions (1) Compare data … (High when INVOUT = 1).” 13-9 13.7 PWM &...

  • Page 349

    24-5 24.5.3 External Clock Input AC Characteristics AP-31 Appendix D: Initialization Routine Sample code comment deleted (under 3.3 MHZ system clock) AP-32 Description deleted (System clock is 3.3 MHz ...) Section added AP-33 Appendix E: S1C17001 Mask ROM Code Development...

  • Page 350

    12/F, Dawning Mansion, Keji South 12th Road, Phone: +49-89-14005-0 FAX: +49-89-14005-110 Hi- Tech Park, Shenzhen Phone: +86-755-2699-3828 FAX: +86-755-2699-3838 EPSON TAIWAN TECHNOLOGY & TRADING LTD. 14F, No. 7, Song Ren Road, Taipei 110 Phone: +886-2-8786-6688 FAX: +886-2-8786-6660 EPSON SINGAPORE PTE., LTD.

  • Page 351

    S1C17001 TECHNICAL MANUAL SEMICONDUCTOR OPERATIONS DIVISION EPSON Electronic Devices Website http://www.epson.jp/device/semicon_e/ Document code : 411412301 First Issue April, 2008 Revised February 2010 in JAPAN...

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