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QSPI Ch.n Mode Byte Register
Register name
Bit
QSPI_nMB
15–8
7–0
Bits 15–8 XIPACT[7:0]
These bits configure the mode byte for activating an XIP session of the external Flash
memory to be accessed in memory mapped access mode.
Bits 7–0
XIPEXT[7:0]
These bits configure the mode byte for terminating the XIP session of the external Flash
memory being accessed in memory mapped access mode.
Note:
In memory mapped access mode, the mode byte is always output from the LSB first.
When using a Flash memory that expects the mode byte to be output from the MSB first,
write the mode byte to this register in reverse bit order.
15-44
Bit name
Initial
XIPACT[7:0]
0x00
XIPEXT[7:0]
0x00
Seiko Epson Corporation
Reset
R/W
H0
R/W
H0
R/W
Remarks
–
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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