Download Print this page

Epson S1C31D50 Technical Instructions page 369

Cmos 32-bit single chip microcontroller
Hide thumbs Also See for S1C31D50:

Advertisement

21.5.7. FLASH CHECKSUM Start Command
"FLASH CHECKSUM Start" command can be set under "mc_state_idle" state.
"FLASH CHECKSUM Start" command starts checksum calculation to FLASH," the state is moved to
"mc_state_checksum" after the memory check start.
After finishing the memory check, HW Processor makes an interrupt on default and goes to
"mc_state_idle".
Please check PROCESSING bit field in STATUS register, it shows process completed or on processing, and
please check RESULT register, it shows CHECKSUM calculation result after process completed, and
compare with original checksum value.
When state transition is occurred, HW Processor makes an interrupt on default, the interrupt can be
masked by
INTMASK on
Table 21.5.7.1 shows "FLASH CHECKSUM Start" command flow.
Cortex Set HW Processor
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
"21.5.11. Memory Check Function Registers".
Wait STATE = "mc_state_idle"
Wait STATUS.READY = mc_status_ready
Set Memory Check COMMAND
-
COMMAND: "FLASH CHECKSUM Start"
-
MEMADDR
- MEMSIZE
in Memory Check Function Registers(See Table 21.5.11.1)
Set HWPCMDTRG.HWP0TRG
Wait HWPINTF.HWP0IF = 1
Check STATE = "mc_state_checksum", if necessary
Wait HWPINTF.HWP0IF = 1
Check STATE = "mc_state_idle"
Check STATUS register
Get RESULT register
Compare with original checksum value
Figure 21.5.7.1 "FLASH CHECKSUM Start" Command Flow
Seiko Epson Corporation
HW Processor interrupts to cortex
HW Processor interrupts to cortex
21-31

Advertisement

loading