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Write 1 to the I2C_nCTL.TXNACK bit
Read receive data
from the I2C_nRXD register
Figure 16.4.3.2 Master Mode Data Reception Flowchart
Data reception using DMA
By setting the I2C_nRBFDMAEN.RBFDMAENx bit to 1 (DMA transfer request enabled), a DMA
transfer request is sent to the DMA controller and the received data is transferred from the
I2C_nRXD register to the specified memory via DMA Ch.x when the I2C_nINTF.RBFIF bit is set to 1
(receive buffer full).
This automates the data receiving procedure Steps 5, 7, and 9 described above.
The transfer source/destination and control data must be set for the DMA controller and the
relevant DMA channel must be enabled to start a DMA transfer in advance. For more information on
DMA, refer to the "DMA Controller" chapter.
Table 16.4.3.1 DMA Data Structure Configuration Example (for Data Reception)
Item
End pointer
Transfer source
Transfer
destination
Control data
dst_inc
dst_size
src_inc
src_size
R_power
n_minus_1
cycle_ctrl
16-10
Data reception
No
One-byte reception?
Yes
Write 1 to the I2C_nCTL.TXNACK bit
Write 1 to the I2C_nCTL.TXSTART bit
Wait for an interrupt request
(I2C_nINTF.TBEIF = 1)
Write slave address and READ(1) to
the I2C_nTXD register
Wait for an interrupt request
(I2C_nINTF.RBFIF = 1 or I2C_nINTF.NACKIF = 1)
I2C_nINTF.RBFIF = 1 ?
Yes
Yes
Receive last data next?
No
Yes
Last data received?
No
Read receive data
from the I2C_nRXD register
Write 1 to the I2C_nCTL.TXSTOP bit
Wait for an interrupt request
(I2C_nINTF.STOPIF = 1)
End
I2C_nRXD register address
Memory address to which the last received data is stored
0x0 (+1)
0x0 (byte)
0x3 (no increment)
0x0 (byte)
0x0 (arbitrated for every transfer)
Number of receive data
0x1 (basic transfer)
Seiko Epson Corporation
No
Retry?
No
Write 1 to the I2C_nCTL.TXSTOP bit
Setting example
S1C31D50 TECHNICAL MANUAL
Yes
(Rev. 1.00)
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