Advertisement
6.2. Operations
6.2.1. Initialization
The DMAC should be initialized with the procedure shown below.
1. Set the data structure base address to the DMACCPTR register.
2. Configure the data structure for the channels to be used.
Set the control data.
-
Set the transfer source end pointer.
-
Set the transfer destination end pointer.
-
3. Set the DMACCFG.MSTEN bit to 1.
4. Configure the DMACRMSET and DMACRMCLR registers.
5. Configure the DMACENSET and DMACENCLR registers.
6. Configure the DMACPASET and DMACPACLR registers.
7. Configure the DMACPRSET and DMACPRCLR registers.
8. Set the following registers when using the interrupt:
Write 1 to the interrupt flags in the DMACENDIF and DMACERRIF registers.
-
Configures the DMACENDIESET/DMACENDIECLR and DMACERRIESET/DMACERRIECLR registers.
-
9. Set the DMA request enable bits of the peripheral circuits that use DMA transfer to 1.
10. To issue a software DMA request to Ch.n, write 1 to the DMACSWREQ.SWREQn bit.
6.3. Priority
If DMA requests are issued to two or more channels, the DMA transfers are performed in order from
the highest- priority channel. The channel of which the priority level is set to 1 by the
DMACPRSET.PRSETn bit has the highest priority. If two or more channels have been set to the same
priority level, the smaller channel number takes precedence.
6.4. Data Structure
To perform DMA transfers, a data structure that contains basic transfer control information must be
provided. The data structure consists of two blocks, primary data structure and alternate data
structure, and one of them is used according to the DMA transfer mode.
The data structure can be located at an arbitrary address in the RAM area by setting the base address to
the DMAC- CPTR.CPTR[31:0] bits.
The data structure for each channel consists of a transfer source end pointer, a transfer destination end
pointer, and control data. An area of 16 bytes × 2 is allocated in the RAM for each channel.
The whole size of the data structure and the alternate data structure base address depend on the
number of channels implemented.
Table 6.4.1 Data Structure Size According to Number of Channels Implemented
Number of
Data
channels
structure
implemented
size
1
32 bytes
2
64 bytes
3 to 4
128 bytes
5 to 8
256 bytes
9 to 16
512 bytes
16 to 32
1,024 bytes
6-2
(Configure masks for DMA transfer requests from peripheral circuits)
Primary data structure
base address
DMACCPTR.CPTR[31:0] (CPTR[4:0] = 0x00)
DMACCPTR.CPTR[31:0] (CPTR[5:0] = 0x00)
DMACCPTR.CPTR[31:0] (CPTR[6:0] = 0x00)
DMACCPTR.CPTR[31:0] (CPTR[7:0] = 0x00)
DMACCPTR.CPTR[31:0] (CPTR[8:0] = 0x000)
DMACCPTR.CPTR[31:0] (CPTR[9:0] = 0x000)
Seiko Epson Corporation
(Enable DMAC)
(Enable channels used)
(Select data structure used)
(Set priorities)
(Clear interrupt flags)
(Enable/disable interrupts)
Alternate data structure
base address
DMACCPTR.CPTR[31:0] + 0x010
DMACCPTR.CPTR[31:0] + 0x020
DMACCPTR.CPTR[31:0] + 0x040
DMACCPTR.CPTR[31:0] + 0x080
DMACCPTR.CPTR[31:0] + 0x100
DMACCPTR.CPTR[31:0] + 0x200
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Advertisement
