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I2C Ch.n Interrupt Enable Register
Register name
Bit
I2C_nINTE
15–8
7
6
5
4
3
2
1
0
Bits 15–8
Reserved
Bit 7
BYTEENDIE
Bit 6
GCIE
Bit 5
NACKIE
Bit 4
STOPIE
Bit 3
STARTIE
Bit 2
ERRIE
Bit 1
RBFIE
Bit 0
TBEIE
These bits enable I2C interrupts.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
The following shows the correspondence between the bit and interrupt:
I2C_nINTE.BYTEENDIE bit:
I2C_nINTE.GCIE bit:
I2C_nINTE.NACKIE bit:
I2C_nINTE.STOPIE bit:
I2C_nINTE.STARTIE bit:
I2C_nINTE.ERRIE bit:
I2C_nINTE.RBFIE bit:
I2C_nINTE.TBEIE bit:
I2C Ch.n Transmit Buffer Empty DMA Request Enable Register
Register name
Bit
I2C_nTBEDMAEN
15–0
Bits 15–0
TBEDMAEN[15:0]
These bits enable the I2C to issue a DMA transfer request to the corresponding DMA
controller channel (Ch.0–Ch.15) when a transmit buffer empty state has occurred.
1 (R/W): Enable DMA transfer request
0 (R/W): Disable DMA transfer request
Each bit corresponds to a DMA controller channel. The high-order bits for the
unimplemented channels are ineffective.
16-26
Bit name
Initial
–
0x00
BYTEENDIE
0
GCIE
0
NACKIE
0
STOPIE
0
STARTIE
0
ERRIE
0
RBFIE
0
TBEIE
0
End of transfer interrupt
General call address reception interrupt
NACK reception interrupt
STOP condition interrupt
START condition interrupt
Error detection interrupt
Receive buffer full interrupt
Transmit buffer empty interrupt
Bit name
Initial
TBEDMAEN[15:0]
0x0000
Seiko Epson Corporation
Reset
R/W
–
R
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
Reset
R/W
H0
R/W
Remarks
–
Remarks
–
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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