Epson S1C31D50 Technical Instructions page 214

HADDR
HTRANS
HREADY
HRDATA
fifo_read_level
QSPI_nMOD register
CPOL bit
CPHA bit
1
1
QSPICLKn
0 0
QSDIOn[3:0]
HCLK
HADDR
HTRANS
HSIZE
HREADY
HRDATA
fifo_read_level
QSPI_nMOD register
CPOL bit CPHA bit
1
1
QSPICLKn
0
0
QSDIOn[3:0]
Figure 15.5.6.1 Data Receiving Operation in Memory Mapped Access Mode - First 32-bit Read
15-20
HCLK
HSEL
n
2
HSIZE
2
(high-order 8/16 bits)
HSEL
Dummy cycle
Seiko Epson Corporation
0
Address cycle
(low-order 16 bits)
0 1
Data cycle 2
Data cycle 1
(prefetching)
Address cycle
Dummy
cycle
n
0 1 2
Data cycle 3
(prefetching)
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)