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R_power
Set the arbitration cycle during successive data transfer.
Arbitration cycle (2
When the DMAC is performing a successive transfer, it suspends the data transfer at the cycle set
with R_power. If DMA requests have been issued at that point, the DMAC re-arbitrates them
according to their priorities and then performs a DMA transfer for the channel with the highest
priority.
If the arbitration cycle setting value is larger than the number of successive data transfers, successive
data transfers will not be suspended.
n_minus_1
Set the number of DMA transfers to be executed successively.
Number of successive transfers (N) = n_minus_1 + 1
When the set number of successive transfers has completed, a transfer completion interrupt occurs.
cycle_ctrl
Set the DMA transfer mode. For detailed information on each transfer mode, refer to Section 6.5,
"DMA Transfer Mode."
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
) = 2
R
R_power
Table 6.4.3.5 DMA Transfer Mode
cycle_ctrl
DMA transfer mode
0x7
Peripheral scatter-gather transfer (for alternate data structure)
0x6
Peripheral scatter-gather transfer (for primary data structure)
0x5
Memory scatter-gather transfer (for alternate data structure)
0x4
Memory scatter-gather transfer (for primary data structure)
0x3
Ping-pong transfer
0x2
Auto-request transfer
0x1
Basic transfer
0x0
Stop
Seiko Epson Corporation
6-5
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