Epson S1C31D50 Technical Instructions page 217

QSPI_nMOD register
CPOL bit
CPHA bit
1 1
QSPICLKn
0
0
QSDIOn[3:0]
QSPI_nMOD register
CPOL bit
CPHA bit
1
1
QSPICLKn
0
0
QSDIOn[3:0]
Figure 15.5.6.4 Data Receiving Operation in Memory Mapped Access Mode - First 8/16-bit Read
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
HCLK
HSEL
HADDR
n
HTRANS
2
HSIZE
0/1
HREADY
HRDATA
(high-order 8/16 bits)
HCLK
HSEL
HADDR
HTRANS
HSIZE
HREADY
HRDATA
Dummy cycle
Seiko Epson Corporation
Address cycle
(low-order 16 bits)
Data cycle
Address cycle Dummy
cycle
n
15-23