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Alternate data structure
Ch.31 (alternate)
Ch.30 (alternate)
Ch.29 (alternate)
Ch.28 (alternate)
Ch.27 (alternate)
Ch.26 (alternate)
Ch.25 (alternate)
Ch.24 (alternate)
Ch.23 (alternate)
Ch.22 (alternate)
Ch.21 (alternate)
Ch.20 (alternate)
Ch.19 (alternate)
Ch.18 (alternate)
Ch.17 (alternate)
Ch.16 (alternate)
Ch.15 (alternate)
Ch.14 (alternate)
Ch.13 (alternate)
Ch.12 (alternate)
Ch.11 (alternate)
Ch.10 (alternate)
Ch.9 (alternate)
Ch.8 (alternate)
Ch.7 (alternate)
Ch.6 (alternate)
Ch.5 (alternate)
Ch.4 (alternate)
Ch.3 (alternate)
Ch.2 (alternate)
Ch.1 (alternate)
Ch.0 (alternate)
Figure 6.4.1 Data Structure Address Map (when 32 channels are implemented)
Alternate data structure
Ch.3 (alternate)
Ch.2 (alternate)
Ch.1 (alternate)
Ch.0 (alternate)
Figure 6.4.2 Data Structure Address Map (when 4 channels are implemented)
The alternate data structure base address can be determined from the DMACACPTR.ACPTR[31:0] bits.
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Alternate data structure
Ch.31 (primary)
0x3f0
Ch.30 (primary)
0x3e0
Ch.29 (primary)
0x3d0
Ch.28 (primary)
0x3c0
Ch.27 (primary)
0x3b0
Ch.26 (primary)
0x3a0
Ch.25 (primary)
0x390
Ch.24 (primary)
0x380
Ch.23 (primary)
0x370
Ch.22 (primary)
0x360
Ch.21 (primary)
0x350
Ch.20 (primary)
0x340
Ch.19 (primary)
0x330
Ch.18 (primary)
0x320
Ch.17 (primary)
0x310
Ch.16 (primary)
0x300
Ch.15 (primary)
0x2f0
Ch.14 (primary)
0x2e0
Ch.13 (primary)
0x2d0
Ch.12 (primary)
0x2c0
Ch.11 (primary)
0x2b0
Ch.10 (primary)
0x2a0
Ch.9 (primary)
0x290
Ch.8 (primary)
0x280
Ch.7 (primary)
0x270
Ch.6 (primary)
0x260
Ch.5 (primary)
0x250
Ch.4 (primary)
0x240
Ch.3 (primary)
0x230
Ch.2 (primary)
0x220
Ch.1 (primary)
0x210
Ch.0 (primary)
0x200
Base address set with the DMACCPTR register
Alternate data structure
Ch.3 (primary)
0x070
Ch.2 (primary)
0x060
Ch.1 (primary)
0x050
Ch.0 (primary)
0x040
Base address set with the DMACCPTR register
Seiko Epson Corporation
0x1f0
0x1e0
0x1d0
0x1c0
0x1b0
0x1a0
0x190
0x180
0x170
0x160
0x150
0x140
0x130
0x120
0x110
0x100
0x0f0
0x0e0
0x0d0
0x0c0
0x0b0
0x0a0
0x090
0x080
0x070
0x060
0x050
0x040
0x030
0x020
Transfer destination end pointer
0x010
Transfer source end pointer
0x000
Offset
Reserved
0x030
Control data
0x020
Transfer destination end pointer
0x010
Transfer source end pointer
0x000
Offset
Reserved
Control data
0x00c
0x008
0x004
0x000
6-3
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