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10. Wait for a STOP condition interrupt (I2C_nINTF.STOPIF bit = 1).
Clear the I2C_nINTF.STOPIF bit by writing 1 after the interrupt has occurred.
Data sending operations
Generating a START condition
The I2C Ch.n starts generating a START condition when the I2C_nCTL.TXSTART bit is set to 1. When
the generating operation has completed, the I2C Ch.n clears the I2C_nCTL.TXSTART bit to 0 and sets
both the I2C_nINTF.STARTIF and I2C_nINTF.TBEIF bits to 1.
Sending slave address and data
If the I2C_nINTF.TBEIF bit = 1, a slave address or data can be written to the I2C_nTXD register. The
I2C Ch.n pulls down SCL to low and enters standby state until data is written to the I2C_nTXD
register. The writing operation triggers the I2C Ch.n to send the data to the shift register
automatically and to output eight clock pulses and data bits to the I
When the slave device returns an ACK as the response, the I2C_nINTF.TBEIF bit is set to 1. After
this interrupt occurs, the subsequent data may be sent or a STOP/repeated START condition may
be issued to terminate transmission. If the slave device returns NACK, the I2C_nINTF.NACKIF bit
is set to 1 without setting the I2C_nINTF.TBEIF bit.
Generating a STOP/repeated START condition
After the I2C_nINTF.TBEIF bit is set to 1 (transmit buffer empty) or the I2C_nINTF.NACKIF bit is set
to 1 (NACK received), setting the I2C_nCTL.TXSTOP bit to 1 generates a STOP condition. When the
bus free time (t
BUF
been generated, the I2C_nCTL.TXSTOP bit is cleared to 0 and the I2C_nINTF.STOPIF bit is set to 1.
When setting the I2C_nCTL.TXSTART bit to 1 while the I2C_nINTF.TBEIF bit = 1 (transmit buffer
empty) or the I2C_nINTF.NACKIF bit = 1 (NACK received), the I2C Ch.n generates a repeated START
condition. When the repeated START condition has been generated, the I2C_nINTF.STARTIF and
I2C_nINTF. TBEIF bits are both set to 1 same as when a START condition has been generated.
Standby state (SCL = low)
TXSTART = 1
Saddr/ W → TXD[7:0]
2
S
Saddr/W
A
I
C bus
TXSTART = 0
STARTIF = 1
TBEIF = 1
A
NACKIF = 1
A
NACKIF = 1
A
NACKIF = 1
TXSTOP = 0
STOPIF = 1
Figure 16.4.2.1 Example of Data Sending Operations in Master Mode
16-6
defined in the I
C Specifications) has elapsed after the STOP condition has
2
Data 1 → TXD[7:0]
Data 2 → TXD[7:0]
Data 1
A
Data 2
TBEIF = 1
TBEIF = 1
TXSTOP = 1
P
TXSTOP = 0
STOPIF = 1
TXSTART = 1
Sr
TXSTART = 0
STARTIF = 1
TBEIF = 1
TXSTART = 1
TXSTOP = 1
S
P
TXSTART = 0
STARTIF = 1
TBEIF = 1
Seiko Epson Corporation
2
Data N → TXD[7:0]
Data N
A
A
TBEIF = 1
TBEIF = 1
A
TBEIF = 1
A
TBEIF = 1
TXSTOP = 0
STOPIF = 1
Software bit operations
Operations by I2C (master mode)
S: START condition, Sr: Repeated START condition, P: STOP condition,
A: ACK, A: NACK, Saddr/W: Slave address + W(0), Data n: 8-bit data
C bus.
TXSTOP = 1
P
TXSTOP = 0
STOPIF = 1
TXSTART = 1
P
TXSTART = 0
STARTIF = 1
TBEIF = 1
TXSTART = 1
TXSTOP = 1
P
S
TXSTART = 0
STARTIF = 1
TBEIF = 1
Hardware bit operations
Operations by the external slave
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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