Epson S1C31D50 Technical Instructions page 191

0 (R/W):
Bit 2 CPHA
Bit 1 CPOL
These bits set the SPI clock phase and polarity. For more information, refer to "SPI Clock
(SPICLKn) Phase and Polarity."
Bit 0 MST
This bit sets the SPIA operating mode (master mode or slave mode).
1 (R/W):
0 (R/W):
Note: The SPIA_nMOD register settings can be altered only when the
SPIA_nCTL.MODEN bit = 0.
14-16
MSB first
Master mode
Slave mode
Seiko Epson Corporation
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)