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21.6. Control Registers
HW Processor Control Register
Register name
Bit
HWPCTL
15–1
0
Bits 15–1
Reserved
Bit 0
HWPEN
This bit enables the HW Processor.
1 (R/W):
0 (R/W):
HW Processor Interrupt Flag Register
Register name
Bit
HWPINTF
15–2
1
0
Bits 15–2
Reserved
Bit 1
HWP1IF(ERRIF)
This bit indicates the HW Processor interrupt cause occurrence status.
1 (R): Cause of interrupt occurred
0 (R): No cause of interrupt occurred
1 (W): Setting prohibited
0 (W): Clear flag
This interrupt shows error
Bit 0
HWP0IF(STIF)
This bit indicates the HW Processor interrupt cause occurrence status.
1 (R): Cause of interrupt occurred
0 (R): No cause of interrupt occurred
1 (W): Setting prohibited
0 (W): Clear flag
This interrupt shows state transition.
HW Processor Interrupt Enable Register
Register name
Bit
HWPINTE
15–1
0
Bits 15–1
Reserved
Bit 0
HWPIE
This bit enables the HW Processor interrupts.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
21-36
Bit name
Initial
–
0x00
HWPEN
0x0
Enable HW Processor operations.
(The operating clock is supplied.)
Disable HW Processor operations.
(The operating clock is stopped.)
Bit name
Initial
–
0x00
HWP1IF(ERRIF)
0x0
HWP0IF(STIF)
0x0
Bit name
Initial
–
0x00
HWPIE
0x0
Seiko Epson Corporation
Reset
R/W
–
R
H0
R/W
Reset
R/W
–
R
H0
R/W
H0
R/W
Reset
R/W
–
R
H0
R/W
Remarks
–
Remarks
–
Remarks
–
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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