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7.2. I/O Cell Structure and Functions
Figure 7.2.1 shows the I/O cell Configuration.
Pull-up/down
Control signal
Input signal
Input control signal
Output signal
Output control signal
Analog signal
Analog control signal
Over voltage tolerant fail-safe type I/O cell
Refer to "Pin Descriptions" in the "Overview" chapter for the cell type, either the over voltage tolerant
fail-safe type I/O cell or the Bold I/O cell, included in each port.
7.2.1. Schmitt Input
The input functions are all configured with the Schmitt interface level. When a port is set to input
disable status (PPORTPxIOEN.PxIENy bit = 0), unnecessary current is not consumed if the Pxy pin is
placed into floating status.
7.2.2. Over Voltage Tolerant Fail-Safe Type I/O Cell
The over voltage tolerant fail-safe type I/O cell allows interfacing without passing unnecessary current
even if a voltage exceeding V
the port is externally biased without supplying V
exceeding the recommended maxi- mum operating power supply voltage to the port.
7.2.3. Pull-Up/Pull-Down
The GPIO port has a pull-up/pull-down function. Either pull-up or pull-down may be selected for each
port individually. This function may also be disabled for the port that does not require pulling up/down.
When the port level is switched from low to high through the pull-up resistor included in the I/O cell or
from high to low through the pull-down resistor, a delay will occur in the waveform rising/falling edge
depending on the time constant by the pull-up/pull-down resistance and the pin load capacitance. The
rising/falling time is commonly determined by the following equation:
t
= -R
× (C
+ C
PR
INU
IN
t
= -R
× (C
+ C
PF
IND
IN
Where
t
:
Rising time (port level = low → high) [second]
PR
t
:
Falling time (port level = high → low) [second]
PF
V
:
High level Schmitt input threshold voltage [V]
T+
V
:
Low level Schmitt input threshold voltage [V]
T-
R
/R
: Pull-up/pull-down resistance [W]
INU
IND
C
:
Pin capacitance [F]
IN
C
: Parasitic capacitance on the board [F]
BOARD
7-2
V
DD
Pull-up/down
control
R
/
V
INU
SS
R
V
IND
DD
* No diode is
connected at
the VDD
V
side.
DD
P
xy
Analog signal
control
V
SS
Figure 7.2.1 I/O Cell Configuration
is applied to the port. Also unnecessary current is not consumed when
DD
) × ln(1 - V
/V
)
BOARD
T+
DD
) × ln(1 - V
/V
)
BOARD
T-
DD
Seiko Epson Corporation
V
Pull-
Pull-up/down
up/down
Control signal
control
V
V
Input signal
Input control signal
Output signal
Output control signal
Analog signal
Analog signal
control
Analog control signal
Standard I/O cell
. However, be sure to avoid applying a voltage
DD
(Eq. 7.1)
DD
R
/
INU
SS
R
IND
DD
V
DD
V
DD
P
xy
V
SS
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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