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2.2. System Reset Controller (SRC)
2.2.1. Overview
SRC is the system reset controller that resets the internal circuits according to the requests from the
reset sources to archive steady IC operations. The main features of SRC are outlined below.
•
Embedded reset hold circuit maintains reset state to boot the system safely while the internal
power supply is un- stable after power on or the oscillation frequency is unstable after the clock
source is initiated.
•
Supports reset requests from multiple reset sources.
#RESET pin
-
POR and BOR
-
Reset request from the CPU
-
Key-entry reset
-
Watchdog timer reset
-
Supply voltage detector reset
-
Peripheral circuit software reset (supports some peripheral circuits only)
-
•
The CPU registers and peripheral circuit control bits will be reset with an appropriate initialization
condition ac- cording to changes in status.
Figure 2.2.1.1 shows the SRC configuration.
#RESET
Reset request from CPU
Key-entry reset
Watchdog timer reset
Supply voltage detector reset
Software reset 0
Software reset n
2.2.2. Input Pin
Table 2.2.2.1 shows the SRC pin.
Pin name
#RESET
The #RESET pin is connected to the noise filter that removes pulses not conforming to the
requirements. An internal pull-up resistor is connected to the #RESET pin, so the pin can be left
open. For the #RESET pin characteristics, refer to "#RESET pin characteristics" in the "Electrical
Characteristics" chapter.
2-4
SRC
Reset request
V
DD
signal
Noise filter
V
POR
SS
BOR
Figure 2.2.1.1 SRC Configuration
Table 2.2.2.1 SRC Pin
I/O
Initial status
I
I (Pull-up)
Seiko Epson Corporation
Clock
generato
r
Boot clock
IOSCCLK
Internal reset signals
(Reset group)
SYSRST_H0
Reset
hold
SYSRST_H1
circuit
SYSRST_S0_0
Reset
SYSRST_S0_n
decoder
Function
Reset input
To CPU and peripheral circuits
To CPU and peripheral circuits
To peripheral circuit 0
To peripheral circuit 1
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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