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SDAC Interrupt Flag Register
Register name
Bit
SDACINTF
15–2
1
0
Bits 15–2
Reserved
Bit 1
ERRIF
This bit indicates the SDAC error interrupt cause occurrence status.
1 (R): Cause of interrupt occurred
0 (R): No cause of interrupt occurred
1 (W): Clear flag
0 (W): Ineffective
Bit 0
DATREQIF
This bit indicates the SDAC data request interrupt cause occurrence status.
1 (R): Cause of interrupt occurred
0 (R): No cause of interrupt occurred
1 (W): Clear flag
0 (W): Ineffective
*This register is used by the HW Processor. This register should not be written while the HW Processor is
enabled.
SDAC Interrupt Enable Register
Register name
Bit
SDACINTE
15–2
1
0
Bits 15–2
Reserved
Bit 1
ERRIE
This bit enables the SDAC error interrupt.
0 (R/W): Disable interrupt
Bit 0
DATREQIE
This bit enables the SDAC data request interrupt.
0 (R/W): Disable interrupt
*This register is used by the HW Processor. This register should not be written while the HW Processor is
enabled.
21-40
Bit name
Initial
–
0x00
ERRIF
0x0
DATREQIF
0x0
Bit name
Initial
–
0x00
ERRIE
0x0
DATREQIE
0x0
Seiko Epson Corporation
Reset
R/W
–
R
H0
R/W
H0
R/W
Reset
R/W
–
R
H0
R/W
H0
R/W
Remarks
–
Remarks
–
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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