Epson S1C31W74 Technical Manual

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CMOS 32-BIT SINGLE CHIP MICROCONTROLLER

S1C31W74

Technical Manual

Rev. 1.1

Table of Contents

Summary of Contents for Epson S1C31W74

Page 1 CMOS 32-BIT SINGLE CHIP MICROCONTROLLER S1C31W74 Technical Manual Rev. 1.1...
Page 2 2. This evaluation board/kit or development tool is intended for use by an electronic engineer and is not a consumer product. The user should use it properly and in a safe manner. Seiko Epson does not assume any responsibility or liability of any kind of damage and/or fire caused by its use.
Page 3 PREFACE Preface This is a technical manual for designers and programmers who develop a product using the S1C31W74. This document describes the functions of the IC, embedded peripheral circuit operations, and their control methods. Notational conventions and symbols in this manual Register address Peripheral circuit chapters do not provide control register addresses.
Page 4: Table Of Contents
3.2 CPU ..........................3-1 3.3 Debugger ........................3-1 3.3.1 List of Debugger Input/Output Pins ..............3-1 3.3.2 External Connection ..................3-1 3.4 Reference Documents ....................3-2 4 Memory and Bus ......................4-1 4.1 Overview ......................... 4-1 Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 5 DMAC Request Mask Clear Register ..................6-12 DMAC Enable Set Register ...................... 6-12 DMAC Enable Clear Register ....................6-12 DMAC Primary-Alternate Set Register ..................6-12 DMAC Primary-Alternate Clear Register .................. 6-13 DMAC Priority Set Register ...................... 6-13 Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 6 8.1 Overview ......................... 8-1 8.2 Peripheral Circuit I/O Function Assignment ..............8-1 8.3 Control Registers ......................8-2 Pxy–xz Universal Port Multiplexer Setting Register ..............8-2 9 Watchdog Timer (WDT2) ....................9-1 9.1 Overview ......................... 9-1 Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 7 11.4.2 SVD2 Operations ................... 11-4 11.5 SVD2 Interrupt and Reset .................... 11-5 11.5.1 SVD2 Interrupt ....................11-5 11.5.2 SVD2 Reset ....................11-5 11.6 Control Registers ......................11-6 SVD2 Ch.n Clock Control Register ..................11-6 Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 8 13.6 Receive Errors ......................13-8 13.6.1 Framing Error ....................13-8 13.6.2 Parity Error ..................... 13-9 13.6.3 Overrun Error ....................13-9 13.7 Interrupts ........................13-9 13.8 DMA Transfer Requests ....................13-9 13.9 Control Registers ......................13-10 Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 9 15.3 Clock Settings ......................15-6 15.3.1 QSPI Operating Clock ................... 15-6 15.3.2 Clock Supply During Debugging ..............15-7 15.3.3 QSPI Clock (QSPICLKn) Phase and Polarity ..........15-7 15.4 Data Format ......................... 15-8 15.5 Operations ........................15-9 Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 10 I2C Ch.n Mode Register ......................16-19 I2C Ch.n Baud-Rate Register ....................16-19 I2C Ch.n Own Address Register ..................... 16-20 I2C Ch.n Control Register ....................... 16-20 I2C Ch.n Transmit Data Register ..................... 16-21 Seiko Epson Corporation viii S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 11 18.4.4 Output in Melody Mode ................. 18-7 18.5 Interrupts ........................18-9 18.6 DMA Transfer Requests ....................18-10 18.7 Control Registers ......................18-10 SNDA Clock Control Register ....................18-10 SNDA Select Register ......................18-11 SNDA Control Register ......................18-12 Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 12 20.4.5 LCD Contrast Adjustment ................20-7 20.5 Operations ........................20-7 20.5.1 Initialization ....................20-7 20.5.2 Display On/Off ....................20-8 20.5.3 Inverted Display ..................... 20-8 20.5.4 Drive Duty Switching ..................20-8 20.5.5 Drive Waveforms ................... 20-10 Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 13 22.3 Clock Settings ......................22-3 22.4 USB Power Supply ...................... 22-4 22.5 Operations ........................22-4 22.5.1 Initialization ....................22-4 22.5.2 Settings when V is Disconnected ............. 22-6 22.5.3 Transaction Control ..................22-7 Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 14 23.3 Current Consumption ....................23-2 23.4 System Reset Controller (SRC) Characteristics ............23-4 23.5 Clock Generator (CLG) Characteristics................ 23-5 23.6 Flash Memory Characteristics ..................23-6 23.7 Input/Output Port (PPORT) Characteristics ..............23-7 Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 15 B.1 Operating Status Configuration Examples for Power Saving ........AP-B-1 B.2 Other Power Saving Methods ..................AP-B-2 Appendix C Mounting Precautions ................AP-C-1 Appendix D Measures Against Noise ................ AP-D-1 Revision History Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL xiii (Rev. 1.1)
Page 16: Overview
1 OVERVIEW 1 Overview The S1C31W74 is a 32-bit MCU with an Arm Cortex -M0+ processor included that features low-power opera- ® ® tion. It incorporates a lot of serial interface circuits and is suitable for various kinds of battery-driven controller ap- plications.
Page 17 IOSC = OFF, OSC1 = ON, OSC3 = OFF, RTC = ON HALT mode 1.7 µA OSC1 = 32 kHz 7.7 µA OSC1 = 32 kHz, LCD = ON (no panel load) Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 18: Block Diagram
TOUT10–11 RFIN0 16-bit PWM timer CAP00–01 R/F converter REF0 (T16B) CAP10–11 (RFC) SENA0 2 Ch. 1 Ch. EXCL00–01 SENB0 EXCL10–11 RFCLKO0 UART USIN0–1 (UART2) USOUT0–1 2 Ch. Figure 1.2.1 S1C31W74 Block Diagram Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 19: Pins
UPMUX UPMUX UPMUX UPMUX QSDIO03 MON) N.C. USB_DM USB_DP V N.C. SPICLK0 SENB0 REF0 RFIN0 EXCL10 EXCL11 OSC3 OSC4 UPMUX UPMUX UPMUX UPMUX UPMUX #QSPISS0 Figure 1.3.1.1 S1C31W74 Pin Configuration Diagram (VFBGA8H-181) Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 20: Pad Configuration Diagram
USB_DP USB_DP USB_DM USB_DM 5.480 mm Figure 1.3.2.1 S1C31W74 Pad Configuration Diagram Pad opening: Pad No. 1–36, 83–127 X = 68 µm, Y = 80 µm Pad No. 49–78, 128–167 X = 80 µm, Y = 68 µm Pad No. 37, 38, 81, 82 X = 76 µm, Y = 90 µm...
Page 21 1 OVERVIEW Table 1.3.2.1 S1C31W74 Pad Coordinates X µm Y µm X µm Y µm X µm Y µm X µm Y µm -2,424.0 -2,334.5 2,649.5 -1,898.0 2,272.2 2,329.5 -2,654.5 2,056.0 -2,344.0 -2,334.5 2,649.5 -1,768.0 2,172.2 2,329.5 -2,654.5 1,976.0 -2,264.0 -2,334.5 2,649.5 -1,638.0...
Page 22: Pin Descriptions
User-selected I/O (universal port multiplexer) Hi-Z – I/O port BZOUT Sound generator output UPMUX User-selected I/O (universal port multiplexer) Hi-Z – I/O port #BZOUT Sound generator inverted output UPMUX User-selected I/O (universal port multiplexer) Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 23 UPMUX User-selected I/O (universal port multiplexer) COM20 LCD common output SEG83 LCD segment output Hi-Z I/O port ✓ UPMUX User-selected I/O (universal port multiplexer) COM21 LCD common output SEG82 LCD segment output Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 24 Hi-Z I/O port ✓ SEG60 LCD segment output Hi-Z I/O port ✓ SEG59 LCD segment output Hi-Z I/O port ✓ SEG58 LCD segment output Hi-Z I/O port ✓ SEG57 LCD segment output Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 25 TOUTn0/CAPn0 n = 0, 1 T16B Ch.n PWM output/capture input 0 (T16B) TOUTn1/CAPn1 T16B Ch.n PWM output/capture input 1 Note: Do not assign a function to two or more pins simultaneously. Seiko Epson Corporation 1-10 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 26: Power Supply, Reset, And Clocks
For the V operating voltage range and recommended external parts, refer to “Recommended Operating Condi- tions, Power supply voltage V ” in the “Electrical Characteristics” chapter and the “Basic External Connection Diagram” chapter, respectively. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 27: D1 Regulator Operation Mode
6. Write a value other than 0x0096 to the SYSPROT.PROT[15:0] bits. (Set system protection) Note: After the voltage mode has been switched, correct the RTC, as the RTC operating clock is also stopped for the period set using the CLGOSC1.OSC1WT[1:0] bits. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 28: System Reset Controller (Src)
#RESET pin, so the pin can be left open. For the #RESET pin characteris- tics, refer to “#RESET pin characteristics” in the “Electrical Characteristics” chapter. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 29: Reset Sources
Table 2.2.4.1 lists the reset groups. For the reset group to initialize the registers and con- trol bits, refer to the “CPU and Debugger” chapter or “Control Registers” in each peripheral circuit chapter. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 30: Clock Generator (Clg)
- The oscillator and clock input circuit on/off state can be maintained or changed at SLEEP mode cancelation. • Provides the FOUT function to output an internal clock for driving external ICs or for monitoring the internal state. Figure 2.3.1.1 shows the CLG configuration. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 31: Input/Output Pins
* Indicates the status when the pin is configured for CLG. If the port is shared with the CLG input/output function and other functions, the CLG function must be assigned to the port. For more information, refer to the “I/O Ports” chapter. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 32: Clock Sources
“OSC1 oscillator circuit characteristics” in the “Electrical Characteristics” chapter, respectively. Note: Depending on the circuit board or the crystal resonator type used, an external gate capacitor C and a drain capacitor C may be required. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 33: Operations
Figure 2.3.4.1 shows the relationship be- tween the oscillation start time and the oscillation stabilization waiting time. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 34 (2) CLGOSC1.OSC1BUP bit = 1 (startup boosting operation enabled) Oscillator circuit enable (CLGOSC.OSC1EN) Oscillation inverter INV1B[1:0] setting gain INV1N[1:0] setting gain Oscillation waveform Startup boosting Normal operation operation Figure 2.3.4.2 Operation Example when the Oscillation Startup Control Circuit is Used Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 35 0x0096 to the SYSPROT.PROT[15:0] bits before the register setting can be altered. For the transition between the operating modes including the system clock switching, refer to “Operating Mode.” Seiko Epson Corporation 2-10 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 36 2. Configure the following CLGFOUT register bits: - CLGFOUT.FOUTSRC[1:0] bits (Select clock source) - CLGFOUT.FOUTDIV[2:0] bits (Set clock division ratio) - Set the CLGFOUT.FOUTEN bit to 1. (Enable clock external output) Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 2-11 (Rev. 1.1)
Page 37 7. The OSC1 oscillation stops if the CLGINTF.OSC1STPIF bit = 1 after an interrupt occurs. If the CLGOSC1.OSDRB bit = 1, the hardware restarts the OSC1 oscillator circuit. Note: Enabling the oscillation stop detection function increase the oscillation stop detector current (I OSD1 Seiko Epson Corporation 2-12 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 38: Operating Mode
0 keeps operating, so the peripheral circuits with the clock being supplied can also operate. By setting this mode when no software processing and peripheral circuit operations are required, power consumption can be less than HALT mode. The RAM retains data even in SLEEP mode. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 2-13 (Rev. 1.1)
Page 39 The conditions listed below generate the HALT/SLEEP cancelation signal to cancel HALT or SLEEP mode and put the CPU into RUN mode. • Interrupt request from a peripheral circuit • NMI from the watchdog timer • Reset request Seiko Epson Corporation 2-14 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 40: Interrupts
Bits 3–2 Reserved Bits 1–0 REGMODE[1:0] These bits control the V regulator operating mode. Table 2.6.1 Internal Regulator Operating Mode PWGACTL.REGMODE[1:0] bits Operating mode Economy mode Normal mode Reserved Automatic mode Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 2-15 (Rev. 1.1)
Page 41: Clg System Clock Control Register
These bits set the division ratio of the clock source to determine the SYSCLK frequency. Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the SYSCLK clock source. When a currently stopped clock source is selected, it will automatically start oscillating or clock input. Seiko Epson Corporation 2-16 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 42: Clg Oscillation Control Register
Stop oscillating or clock input Each bit corresponds to the clock source as follows: CLGOSC.EXOSCEN bit: EXOSC clock input CLGOSC.OSC3EN bit: OSC3 oscillator circuit CLGOSC.OSC1EN bit: OSC1 oscillator circuit CLGOSC.IOSCEN bit: IOSC oscillator circuit Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 2-17 (Rev. 1.1)
Page 43: Clg Iosc Control Register
Remarks CLGOSC1 – – – OSDRB R/WP OSDEN R/WP OSC1BUP R/WP – – 10–8 CGI1[2:0] R/WP 7–6 INV1B[1:0] R/WP 5–4 INV1N[1:0] R/WP 3–2 – – 1–0 OSC1WT[1:0] R/WP Bit 15 Reserved Seiko Epson Corporation 2-18 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 44 These bits set the oscillation inverter gain applied at normal operation of the OSC1 oscillator circuit. Table 2.6.7 Setting Oscillation Inverter Gain at OSC1 Normal Operation CLGOSC1.INV1N[1:0] bits Inverter gain Max. ↑ ↓ Min. Bits 3–2 Reserved Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 2-19 (Rev. 1.1)
Page 45: Clg Osc3 Control Register
IOSCTERIF Cleared by writing 1. – – – (reserved) OSC1STPIF Cleared by writing 1. IOSCTEDIF – – – OSC3STAIF Cleared by writing 1. OSC1STAIF IOSCSTAIF Bits 15–9, 7, 6, 3 Reserved Seiko Epson Corporation 2-20 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 46: Clg Interrupt Enable Register
CLGINTE.IOSCTEDIE bit: IOSC oscillation auto-trimming completion interrupt CLGINTE.OSC3STAIE bit: OSC3 oscillation stabilization waiting completion interrupt CLGINTE.OSC1STAIE bit: OSC1 oscillation stabilization waiting completion interrupt CLGINTE.IOSCSTAIE bit: IOSC oscillation stabilization waiting completion interrupt Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 2-21 (Rev. 1.1)
Page 47: Clg Fout Control Register
0 (R/W): Disable external output Note: Since the FOUT signal generated is out of sync with writings to the CLGFOUT.FOUTEN bit, a glitch may occur when the FOUT output is enabled or disabled. Seiko Epson Corporation 2-22 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 48: Cpu And Debugger
For the recommended pull-up resistor value, refer to “Recommended Operating Conditions, Debug pin pull-up re- sistors R ” in the “Electrical Characteristics” chapter. R and R are not required when using the debug DBG1–2 DBG1 DBG2 pins as general-purpose I/O port pins. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 49: Reference Documents
Architecture Reference Manual ® 2. Cortex -M0+Technical Reference Manual ® 3. Cortex -M0+ Devices Generic User Guide ® These documents can be downloaded from the document site of Arm Ltd. https://developer.arm.com/documentation Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 50: Memory And Bus
Memory mapped access area for external Flash memory (1M bytes) (Device size: 32 bits) 0x0008 0000 0x0007 ffff Flash area (512K bytes) (Device size: 32 bits) 0x0000 0000 Figure 4.1.1 Memory Map Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 51: Bus Access Cycle
The number of bus access cycles for reading can be configured using the FLASHCWAIT.RDWAIT[1:0] bits. Select a setting for higher frequency than the system clock. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 52: Flash Programming
SVD2 Ch.0 Clock Control Register (SVD2) Ch.0 0x4000 0102 SVD2_0CTL SVD2 Ch.0 Control Register 0x4000 0104 SVD2_0INTF SVD2 Ch.0 Status and Interrupt Flag Register 0x4000 0106 SVD2_0INTE SVD2 Ch.0 Interrupt Enable Register Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 53 0x4000 026a PPORTP6CHATEN P6 Port Chattering Filter Enable Register 0x4000 026c PPORTP6MODSEL P6 Port Mode Select Register 0x4000 026e PPORTP6FNCSEL P6 Port Function Select Register 0x4000 0270 PPORTP7DAT P7 Port Data Register Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 54 0x4000 03b0 SPIA_0MOD SPIA Ch.0 Mode Register (SPIA) Ch.0 0x4000 03b2 SPIA_0CTL SPIA Ch.0 Control Register 0x4000 03b4 SPIA_0TXD SPIA Ch.0 Transmit Data Register 0x4000 03b6 SPIA_0RXD SPIA Ch.0 Receive Data Register Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 55 UART2 Ch.1 Mode Register 0x4000 0604 UART2_1BR UART2 Ch.1 Baud-Rate Register 0x4000 0606 UART2_1CTL UART2 Ch.1 Control Register 0x4000 0608 UART2_1TXD UART2 Ch.1 Transmit Data Register 0x4000 060a UART2_1RXD UART2 Ch.1 Receive Data Register Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 56 LCD32B Clock Control Register 0x4000 0802 LCD32BCTL LCD32B Control Register 0x4000 0804 LCD32BTIM1 LCD32B Timing Control Register 1 0x4000 0806 LCD32BTIM2 LCD32B Timing Control Register 2 0x4000 0808 LCD32BPWR LCD32B Power Control Register Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 57 USB EPa Interrupt Enable Register 0x2040 0065 USBEPbINTE USB EPb Interrupt Enable Register 0x2040 0066 USBEPcINTE USB EPc Interrupt Enable Register 0x2040 0100 USBFIFODAT USB FIFO Data Register 0x2040 0104 USBDBGRAMDAT USB Debug RAM Data Register Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 58: System-Protect Function
4.8 Memory Mapped Access Area For External Flash Memory This area is used to read data from the external Flash memory via the quad synchronous serial interface. For more information, refer to the “Quad Synchronous Serial Interface” chapter. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 59: Control Registers
Notes: • Be sure to set the FLASHCWAIT.RDWAIT[1:0] bits before the system clock is configured. • When the FLASHCWAIT.RDWAIT[1:0] bit setting is altered from 0x2 to 0x1, add two NOP instructions immediately after that. Program example: FLASHC->WAIT_b.RDWAIT = 1; asm(“NOP”); asm(“NOP”); CLG->OSC_b.IOSCEN = 0; Seiko Epson Corporation 4-10 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 60: Interrupt
• IOSC oscillation stabilization waiting completion • OSC1 oscillation stabilization waiting completion • OSC3 oscillation stabilization waiting completion • OSC1 oscillation stop • IOSC oscillation auto-trimming completion • IOSC oscillation auto-trimming error Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 61 • Transmit buﬀer empty VTOR + 0x80 IR remote controller • Compare AP interrupt • Compare DB VTOR + 0x84 LCD driver interrupt Frame VTOR + 0x88 16-bit timer Ch.3 interrupt Underﬂow Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 62: Vector Table Offset Address (Vtor)
Note: To prevent occurrence of unnecessary interrupts, the corresponding interrupt flag should be cleared before setting the interrupt enable bit to 1 (interrupt enabled) and before terminating the interrupt handler routine. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 63: Nmi
The watchdog timer embedded in this IC can generate a non-maskable interrupt (NMI). This interrupt takes prece- dence over other interrupts and is unconditionally accepted by the CPU. For detailed information on generating NMI, refer to the “Watchdog Timer” chapter. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 64: Dma Controller (Dmac)
• Priority level for each channel is selectable from two levels. • DMA transfers are allowed even if the CPU is placed into HALT mode. Figure 6.1.1 shows the configuration of the DMAC. Table 6.1.1 DMAC Channel Configuration of S1C31W74 Item S1C31W74 Number of channels 4 channels (Ch.0 to Ch.3)
Page 65: Operations
256 bytes DMACCPTR.CPTR[31:0] (CPTR[7:0] = 0x00) DMACCPTR.CPTR[31:0] + 0x080 9 to 16 512 bytes DMACCPTR.CPTR[31:0] (CPTR[8:0] = 0x000) DMACCPTR.CPTR[31:0] + 0x100 17 to 32 1,024 bytes DMACCPTR.CPTR[31:0] (CPTR[9:0] = 0x000) DMACCPTR.CPTR[31:0] + 0x200 Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 66: Transfer Source End Pointer
6.4.2 Transfer Destination End Pointer Set the address to which the last transfer data is written. The address for writing transfer data should be set as it is if the transfer destination address is not incremented. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 67 When the DMAC is performing a successive transfer, it suspends the data transfer at the cycle set with R_pow- er. If DMA requests have been issued at that point, the DMAC re-arbitrates them according to their priorities and then performs a DMA transfer for the channel with the highest priority. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 68: Dma Transfer Mode
DMA transfer 1 DMA transfer 2 DMA transfer 3 DMA transfer 4 DMA transfer 7 DMA transfer 8 operation DMACENDIF.ENDIFn DMA transfer request Figure 6.5.2.1 Auto-Request Transfer Operation Example (N = 8, 2 = 2) Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 69: Ping-Pong Transfer
5. Set cycle_ctrl to 0x0 after a DMA transfer completion interrupt has occurred by the next to last task. 6. The DMA transfer is completed when a DMA transfer completion interrupt occurs by the last task. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 70: Memory Scatter-Gather Transfer
Copy the data structure for Task D to the alternate data structure. (cycle_ctrl = 0x1, 2 = 4, N = 4) Task D DMA transfer completion interrupt Figure 6.5.4.2 Memory Scatter-Gather Transfer Operation Example Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 71: Peripheral Scatter-Gather Transfer
Copy the data structure for Task D to the alternate data structure. (cycle_ctrl = 0x1, 2 = 4, N = 4) Task D DMA transfer completion interrupt Figure 6.5.5.1 Peripheral Scatter-Gather Transfer Operation Example Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 72: Dma Transfer Cycle
The DMAC provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the CPU only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For more information on interrupt control, refer to the “Interrupt” chapter. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 73: Control Registers
– 15–8 – 0x00 – – 7–1 – 0x00 – MSTEN – – Bits 31–1 Reserved Bit 0 MSTEN This bit enables the DMA controller. 1 (W): Enable 0 (W): Disable Seiko Epson Corporation 6-10 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 74: Dmac Control Data Base Pointer Register
DMA transfer requests from peripheral circuits have been disabled. 0 (R): DMA transfer requests from peripheral circuits have been enabled. Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented channels are ineffective. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 6-11 (Rev. 1.1)
Page 75: Dmac Request Mask Clear Register
The alternate data structure has been enabled. 0 (R): The primary data structure has been enabled. Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented channels are ineffective. Seiko Epson Corporation 6-12 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 76: Dmac Primary-Alternate Clear Register
ERRIF This bit indicates the DMAC error interrupt cause occurrence status. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 6-13 (Rev. 1.1)
Page 77: Dmac Transfer Completion Interrupt Flag Register
DMAC Error Interrupt Enable Set Register Register name Bit name Initial Reset Remarks DMACERRIESET 31–24 – 0x00 – – 23–16 – 0x00 – 15–8 – 0x00 – 7–1 – 0x00 – ERRIESET Bits 31–1 Reserved Seiko Epson Corporation 6-14 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 78: Dmac Error Interrupt Enable Clear Register
0x00 – ERRIECLR – – Bits 31–1 Reserved Bit 0 ERRIECLR This bit disables DMA error interrupts. 1 (W): Disable interrupt (The DMACERRIESET register is cleared to 0.) 0 (W): Ineffective Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 6-15 (Rev. 1.1)
Page 79: O Ports (Pport)
Note: ‘x’, which is used in the port names Pxy, register names, and bit names, refers to a port group (x = 0, 1, 2, ··· , d) and ‘y’ refers to a port number (y = 0, 1, 2, ··· , 7). Figure 7.1.1 shows the configuration of PPORT. Table 7.1.1 Port Configuration of S1C31W74 Item S1C31W74...
Page 80: I/O Cell Structure And Functions
Falling time (port level = high → low) [second] High level Schmitt input threshold voltage [V] Low level Schmitt input threshold voltage [V] : Pull-up/pull-down resistance [W] Pin capacitance [F] Parasitic capacitance on the board [F] BOARD Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 81: Cmos Output And High Impedance State
• Port pins: High impedance state • Port function: Configured to GPIO This status continues until the ports are configured via software. The debugging function ports are configured for debug signal input/output. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 82 * Steps 1 and 5 are required for the ports with an interrupt function. Step 2 is required for the ports with a chat- tering filter function. Table 7.4.1.1 lists the port status according to the combination of data input/output control and pull-up/down control. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 83: Port Input/Output Control
1. Configure the ports to be used for key-entry reset as general-purpose input ports (refer to “Initial settings when using a port as a general-purpose input port (only for the ports with GPIO function)”). 2. Configure the input pin combination for key-entry reset using the PPORTCLK.KRSTCFG[1:0] bits. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 84: Interrupts
These bits are used to set data to be output from the GPIO port pins. 1 (R/W): Output high level from the port pin 0 (R/W): Output low level from the port pin Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 85: Px Port Enable Register
PPORTPxIOEN.PxIENy bit is set and the port is not pulled up/down. These bits do not affect the pull-up/down control when the port is used as a peripheral I/O function. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 86: Px Port Interrupt Flag Register
PPORTPxMODSEL 15–8 – 0x00 – – 7–0 PxSEL[7:0] 0x00 *1: The bit configuration differs depending on the port group. *2: The initial value may be changed by the port. Bits 15–8 Reserved Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 87: Px Port Function Select Register
Table 7.6.2 Key-Entry Reset Function Settings PPORTCLK.KRSTCFG[1:0] bits key-entry reset Reset when P0[3:0] inputs = all low Reset when P0[2:0] inputs = all low Reset when P0[1:0] inputs = all low Disable Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 88: P Port Interrupt Flag Group Register
A port generated an interrupt 0 (R): No port generated an interrupt The PPORTINTFGRP.PxINT bit is cleared when the interrupt flag for the port that has generated an interrupt is cleared. Seiko Epson Corporation 7-10 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 89: Control Register And Port Function Configuration Of This Ic
RFC Ch.0 SENA0 UPMUX – – – – RFC Ch.0 REF0 UPMUX – – – – RFC Ch.0 RFIN0 UPMUX – – – – *1: Refer to the “Universal Port Multiplexer” chapter. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 7-11 (Rev. 1.1)
Page 90: P1 Port Group
– – REMC2 REMO UPMUX – – – – REMC2 CLPLS UPMUX – – – – RTCA RTC1S UPMUX – – – – *1: Refer to the “Universal Port Multiplexer” chapter. Seiko Epson Corporation 7-12 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 91: P2 Port Group
QSDIO03 – – – – T16B Ch.1 EXCL11 QSPI Ch.0 #QSPISS0 – – – – EXOSC – – – – – – – – – – SVD2 Ch.0 EXSVD0 – – Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 7-13 (Rev. 1.1)
Page 92: P3 Port Group
– UPMUX – – LCD32B COM21/ SEG82 – – UPMUX – – LCD32B COM22/ SEG81 – – UPMUX – – LCD32B COM23/ SEG80 *1: Refer to the “Universal Port Multiplexer” chapter. Seiko Epson Corporation 7-14 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 93: P4 Port Group
– LCD32B COM28/ SEG75 – – – – – – LCD32B COM29/ SEG74 – – – – – – LCD32B COM30/ SEG73 – – – – – – LCD32B COM31/ SEG72 Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 7-15 (Rev. 1.1)
Page 94: P5 Port Group
– – – – – LCD32B SEG67 – – – – – – LCD32B SEG66 – – – – – – LCD32B SEG65 – – – – – – LCD32B SEG64 Seiko Epson Corporation 7-16 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 95: P6 Port Group
– – – – – LCD32B SEG59 – – – – – – LCD32B SEG58 – – – – – – LCD32B SEG57 – – – – – – LCD32B SEG56 Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 7-17 (Rev. 1.1)
Page 96: P7 Port Group
– – – – – LCD32B SEG5 – – – – – – LCD32B SEG4 – – – – – – LCD32B SEG3 – – – – – – LCD32B SEG2 Seiko Epson Corporation 7-18 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 97: P8 Port Group
P8yMUX = 0x3 name GPIO (Function 0) (Function 1) (Function 2) (Function 3) Peripheral Peripheral Peripheral Peripheral – – – – – – LCD32B SEG1 – – – – – – LCD32B SEG0 Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 7-19 (Rev. 1.1)
Page 98: P9 Port Group
P9yMUX = 0x1 P9yMUX = 0x2 P9yMUX = 0x3 name GPIO (Function 0) (Function 1) (Function 2) (Function 3) Peripheral Peripheral Peripheral Peripheral – – – – SVD2 Ch.1 EXSVD1 – – (VBUS_MON) Seiko Epson Corporation 7-20 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 99: Pd Port Group
Peripheral Peripheral Peripheral Peripheral SWCLK – – – – – – – – – – – – – – – – OSC3 – – – – – – OSC4 – – Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 7-21 (Rev. 1.1)
Page 100: Common Registers Between Port Groups
7–4 CLKDIV[3:0] R/WP 3–2 KRSTCFG[1:0] R/WP 1–0 CLKSRC[1:0] R/WP PPORTINTFGRP 15–10 – 0x00 – – (P Port Interrupt Flag P9INT Group Register) P8INT P7INT P6INT P5INT P4INT P3INT P2INT P1INT P0INT Seiko Epson Corporation 7-22 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 101: Universal Port Multiplexer (Upmux)
4. Initialize the peripheral circuit. 5. Set the PPORTPxFNCSEL.PxyMUX[1:0] bits of the I/O port to 0x1. (Select peripheral I/O function 1) 6. Set the PPORTPxMODSEL.PxSELy bit of the I/O port to 1. (Enable peripheral I/O function) Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 102: Control Registers
Note: Do not assign a peripheral input function to two or more I/O ports. Although the I/O ports output the same waveforms when an output function is assigned to two or more I/O port, a skew oc- curs due to the internal delay. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 103: Watchdog Timer (Wdt2)
CLK_WDT2 supply is suspended, the register retains the status before DEBUG mode was entered. If the WDT2CLK.DBRUN bit = 1, the CLK_WDT2 supply is not suspended and WDT2 will keep operating in DEBUG mode. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 104: Operations
1. Write 0x0096 to the SYSPROT.PROT[15:0] bits. (Remove system protection) 2. Write 0xa to the WDT2CTL.WDTRUN[3:0] bits. (Stop WDT2) 3. Write a value other than 0x0096 to the SYSPROT.PROT[15:0] bits. (Set system protection) Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 105: Operations In Halt And Sleep Modes
IOSC OSC1 OSC3 EXOSC 1/65,536 1/128 1/65,536 1/32,768 1/32,768 1/16,384 1/16,384 1/8,192 1/8,192 (Note) The oscillation circuits/external input that are not supported in this IC cannot be selected as the clock source. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 106: Wdt2 Control Register
Always 0x0 is read if a value other than 0xa is written. Since an NMI or reset may be generated immediately after running depending on the counter value, WDT2 should also be reset concurrently when running WDT2. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 107: Wdt2 Counter Compare Match Register
These bits set the NMI/reset generation cycle. The value set in this register is compared with the 10-bit counter value while WDT2 is running, and an NMI or reset is generated when they are matched. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 108: Real-Time Clock (Rtca)
If the port is shared with the RTCA output function and other functions, the RTCA function must be assigned to the port. For more information, refer to the “I/O Ports” chapter. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 10-1 (Rev. 1.1)
Page 109: Clock Settings
· · · · · · · · · · · · 0x3e 59.1 0x7e -1.9 0x3f 60.1 0x7f -1.0 Minimum resolution: 1 ppm, Correction rate range: -61.0 to 60.1 ppm Seiko Epson Corporation 10-2 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 110: Operations
3. Write 1 to the RTCAINTF.ALARMIF bit to clear the alarm interrupt flag. 4. Write 1 to the RTCAINTE.ALARMIE bit to enable alarm interrupts. When the real-time clock counter reaches the alarm time set in Step 2, an alarm interrupt occurs. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 10-3 (Rev. 1.1)
Page 111: Real-Time Clock Counter Operations
The stopwatch consists of 1/100-second and 1/10-second counters and these counters perform counting up in incre- ments of approximate 1/100 and 1/10 seconds with the count-up patterns shown in Figure 10.4.4.1. Seiko Epson Corporation 10-4 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 112: Interrupts
1 Hz counter value. • An alarm interrupt occurs after a lapse of 1/256 second from matching between the AM/PM (in 12H mode), hour, minute, and second counter value and the alarm setting value. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 10-5 (Rev. 1.1)
Page 113: Control Registers
This bit executes the 30-second correction time adjustment function. 1 (W): Execute 30-second correction 0 (W): Ineffective 1 (R): 30-second correction is executing. 0 (R): 30-second correction has finished. (Normal operation) Seiko Epson Corporation 10-6 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 114: Rtca Control Register (High Byte)
1 as well. However, no correcting operation is performed. RTCA Second Alarm Register Register name Bit name Initial Reset Remarks RTCAALM1 – – – 14–12 RTCSHA[2:0] 11–8 RTCSLA[3:0] 7–0 – 0x00 – Bit 15 Reserved Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 10-7 (Rev. 1.1)
Page 115: Rtca Hour/Minute Alarm Register
BCD code. RTCA Stopwatch Control Register Register name Bit name Initial Reset Remarks RTCASWCTL 15–12 BCD10[3:0] – 11–8 BCD100[3:0] 7–5 – – SWRST Read as 0. 3–1 – – – SWRUN Seiko Epson Corporation 10-8 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 116: Rtca Second/1Hz Register
10-second digit and the 1-second digit of the second counter, respectively. The setting/read values are a BCD code within the range from 0 to 59. Note: Be sure to avoid writing to the RTCASEC.RTCSH[2:0]/RTCSL[3:0] bits while the RTCACTLL. RTCBSY bit = 1. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 10-9 (Rev. 1.1)
Page 117: Rtca Hour/Minute Register
1 to 12 in 12H mode or 0 to 23 in 24H mode. Note: Be sure to avoid writing to the RTCAHUR.RTCHH[1:0]/RTCHL[3:0] bits while the RTCACTLL. RTCBSY bit = 1. Bit 7 Reserved Seiko Epson Corporation 10-10 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 118: Rtca Month/Day Register
The day of the week counter is a base-7 counter and the setting/read values are 0x0 to 0x6. Table 10.6.2 lists the correspondence between the count value and day of the week. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 10-11 (Rev. 1.1)
Page 119: Rtca Interrupt Flag Register
The following shows the correspondence between the bit and interrupt: RTCAINTF.RTCTRMIF bit: Theoretical regulation completion interrupt RTCAINTF.SW1IF bit: Stopwatch 1 Hz interrupt RTCAINTF.SW10IF bit: Stopwatch 10 Hz interrupt RTCAINTF.SW100IF bit: Stopwatch 100 Hz interrupt Bits 11–9 Reserved Seiko Epson Corporation 10-12 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 120: Rtca Interrupt Enable Register
The following shows the correspondence between the bit and interrupt: RTCAINTE.RTCTRMIE bit: Theoretical regulation completion interrupt RTCAINTE.SW1IE bit: Stopwatch 1 Hz interrupt RTCAINTE.SW10IE bit: Stopwatch 10 Hz interrupt RTCAINTE.SW100IE bit: Stopwatch 100 Hz interrupt Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 10-13 (Rev. 1.1)
Page 121 RTCAINTE.T1DAYIE bit: 1-day interrupt RTCAINTE.T1HURIE bit: 1-hour interrupt RTCAINTE.T1MINIE bit: 1-minute interrupt RTCAINTE.T1SECIE bit: 1-second interrupt RTCAINTE.T1_2SECIE bit: 1/2-second interrupt RTCAINTE.T1_4SECIE bit: 1/4-second interrupt RTCAINTE.T1_8SECIE bit: 1/8-second interrupt RTCAINTE.T1_32SECIE bit: 1/32-second interrupt Seiko Epson Corporation 10-14 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 122: Supply Voltage Detector (Svd2)
- Continuous operation is also possible. Figure 11.1.1 shows the configuration of SVD2. Table 11.1.1 SVD2 Channel Configuration of S1C31W74 Item S1C31W74 Number of channels 2 channels (Ch.0 and Ch.1)
Page 123: Input Pin And External Connection
SLEEP mode and SVD2 Ch.n stops with the register settings maintained at those before entering SLEEP mode. After the CPU returns to normal mode, CLK_SVD2_n is supplied and the SVD2 Ch.n operation re- sumes. Seiko Epson Corporation 11-2 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 124: Clock Supply During Debugging
SVD2_nCTL.MODEN bit = 1, wait for at least SVD circuit response time before reading the SVD2_nINTF. SVDDT bit (refer to “Supply Voltage Detector Characteristics, SVD circuit response time t ” in the “Electrical Characteristics” chapter). Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 11-3 (Rev. 1.1)
Page 125: Svd2 Operations
Voltage detection operating status SVD2_nINTF.SVDDT Power supply voltage rise detection interrupt : Level set using the SVD2_nCTL.SVDC[4:0] bits : Voltage detection masking time : Voltage detection operation Figure 11.4.2.1 SVD2 Operations Seiko Epson Corporation 11-4 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 126: Svd2 Interrupt And Reset
SVDMD[1:0] Cleared to 0 to set continuous operation mode. MODEN The set value (1) is retained. SVD2_nINTF SVDIF The status (1) before being reset is retained. SVD2_nINTE SVDIE Cleared to 0. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 11-5 (Rev. 1.1)
Page 127: Control Registers
– 2–1 SVDMD[1:0] MODEN Bit 15 VDSEL This bit selects the power supply voltage to be detected by SVD2 Ch.n. 1 (R/WP): Voltage applied to the EXSVDn pin 0 (R/WP): V Seiko Epson Corporation 11-6 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 128 1 (R/W): Enable (Start detection operations) 0 (R/W): Disable (Stop detection operations) After this bit has been altered, wait until the value written is read out from this bit without subsequent operations being performed. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 11-7 (Rev. 1.1)
Page 129: Svd2 Ch.n Status And Interrupt Flag Register
• To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared before enabling interrupts. Seiko Epson Corporation 11-8 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 130: 16-Bit Timers (T16)
• A clock source and clock division ratio for generating the count clock are selectable. • Repeat mode or one-shot mode is selectable. • Can generate counter underflow interrupts. Figure 12.1.1 shows the configuration of a T16 channel. Table 12.1.1 T16 Channel Configuration of S1C31W74 Item S1C31W74 Number of channels 4 channels (Ch.0–Ch.3)
Page 131: Clock Settings
(Set reload data (counter preset data)) 5. Set the following bits when using the interrupt: - Write 1 to the T16_nINTF.UFIF bit. (Clear interrupt flag) - Set the T16_nINTE.UFIE bit to 1. (Enable underflow interrupt) Seiko Epson Corporation 12-2 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 132: Counter Underflow
At the same time the counter stops, the T16_ nCTL.PRUN bit is cleared automatically. Select this mode to stop the counter after an interrupt has occurred once, such as for checking a specific lapse of time. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 12-3 (Rev. 1.1)
Page 133: Counter Value Read
Bits 7–4 CLKDIV[3:0] These bits select the division ratio of the T16 Ch.n operating clock (counter clock). Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the clock source of T16 Ch.n. Seiko Epson Corporation 12-4 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 134: T16 Ch.n Control Register
PRESET MODEN Bits 15–9 Reserved Bit 8 PRUN This bit starts/stops the timer. 1 (W): Start timer 0 (W): Stop timer 1 (R): Timer is running 0 (R): Timer is idle Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 12-5 (Rev. 1.1)
Page 135: T16 Ch.n Reload Data Register
This bit indicates the T16 Ch.n underflow interrupt cause occurrence status. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective Seiko Epson Corporation 12-6 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 136: T16 Ch.n Interrupt Enable Register
This bit enables T16 Ch.n underflow interrupts. 1 (R/W): Enable interrupts 0 (R/W): Disable interrupts Note: To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared before enabling interrupts. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 12-7 (Rev. 1.1)
Page 137: Uart (Uart2)
• Input pin can be pulled up with an internal resistor. • The output pin is configurable as an open-drain output. Figure 13.1.1 shows the UART2 configuration. Table 13.1.1 UART2 Channel Configuration of S1C31W74 Item S1C31W74 Number of channels 2 channels (Ch.0 and Ch.1)
Page 138: Input/Output Pins And External Connections
(Clock source selection) - UART2_nCLK.CLKDIV[1:0] bits (Clock division ratio selection = Clock frequency setting) The UART2 operating clock should be selected so that the baud rate generator will be configured easily. Seiko Epson Corporation 13-2 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 139: Clock Supply In Sleep Mode
(UART2_nMOD.STPB bit = 1). Parity function The parity function is configured using the UART2_nMOD.PREN and UART2_nMOD.PRMD bits. Table 13.4.1 Parity Function Setting UART2_nMOD.PREN bit UART2_nMOD.PRMD bit Parity function Odd parity Even parity Non parity Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 13-3 (Rev. 1.1)
Page 140: Operations
7. Configure the DMA controller and set the following UART2 control bits when using DMA transfer: - Write 1 to the DMA transfer request enable bits in the UART2_nTBEDMAEN and UART2_nRB1FDMAEN registers. (Enable DMA transfer requests) Seiko Epson Corporation 13-4 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 141: Data Transmission
Read the UART2_nINTF.TBEIF bit UART2_nINTF.TBEIF = 1 ? Write transmit data to the UART2_nTXD register Transmit data remained? Wait for an interrupt request (UART2_nINTF.TBEIF = 1) Figure 13.5.2.2 Data Transmission Flowchart Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 13-5 (Rev. 1.1)
Page 142: Data Reception
UART2_nINTF.RB1FIF bit to 1 (receive buffer one byte full). If the sec- ond data is received without reading the first data, the UART2_nINTF.RB2FIF bit is set to 1 (receive buffer two bytes full). Seiko Epson Corporation 13-6 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 143: Irda Interface
Set the UART2_nMOD.IRMD bit to 1 to use the IrDA interface. Data transfer control is identical to that for normal interface even if the IrDA interface function is enabled. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 13-7 (Rev. 1.1)
Page 144: Receive Errors
The interrupt flag will be set when the first data byte already loaded is read out after the data that encountered an error is transferred to the second byte entry of the receive data buffer. Seiko Epson Corporation 13-8 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 145: Parity Error
Transmit buffer empty Transmit buffer empty flag When transmit data written Writing transmit data (UART2_nINTF.TBEIF) to the transmit data buffer is transferred to the shift register Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 13-9 (Rev. 1.1)
Page 146: Control Registers
(Note) The oscillation circuits/external input that are not supported in this IC cannot be selected as the clock source. Note: The UART2_nCLK register settings can be altered only when the UART2_nCTL.MODEN bit = 0. Seiko Epson Corporation 13-10 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 147: Uart2 Ch.n Mode Register
This bit sets the data length. 1 (R/W): 8 bits 0 (R/W): 7 bits Bit 2 PREN This bit enables the parity function. 1 (R/W): Enable parity function 0 (R/W): Disable parity function Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 13-11 (Rev. 1.1)
Page 148: Uart2 Ch.n Baud-Rate Register
Note: If the UART2_nCTL.MODEN bit is altered from 1 to 0 while sending/receiving data, the data being sent/received cannot be guaranteed. When setting the UART2_nCTL.MODEN bit to 1 again after that, be sure to write 1 to the UART2_nCTL.SFTRST bit as well. Seiko Epson Corporation 13-12 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 149: Uart2 Ch.n Transmit Data Register
This bit indicates the receiving status. (See Figure 13.5.3.1.) 1 (R): During receiving 0 (R): Idle Bit 8 TBSY This bit indicates the sending status. (See Figure 13.5.2.1.) 1 (R): During sending 0 (R): Idle Bit 7 Reserved Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 13-13 (Rev. 1.1)
Page 150: Uart2 Ch.n Interrupt Enable Register
UART2_nINTE.PEIE bit: Parity error interrupt UART2_nINTE.OEIE bit: Overrun error interrupt UART2_nINTE.RB2FIE bit: Receive buffer two bytes full interrupt UART2_nINTE.RB1FIE bit: Receive buffer one byte full interrupt UART2_nINTE.TBEIE bit: Transmit buffer empty interrupt Seiko Epson Corporation 13-14 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 151: Uart2 Ch.n Transmit Buffer Empty Dma Request Enable Register
(Ch.0–Ch.15) when a receive buffer one byte full state has occurred. 1 (R/W): Enable DMA transfer request 0 (R/W): Disable DMA transfer request Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented chan- nels are ineffective. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 13-15 (Rev. 1.1)
Page 152: Synchronous Serial Interface (Spia)
• Slave mode is capable of being operated in SLEEP mode allowing wake-up by an SPIA interrupt. • Input pins can be pulled up/down with an internal resistor. Figure 14.1.1 shows the SPIA configuration. Table 14.1.1 SPIA Channel Configuration of S1C31W74 Item S1C31W74 Number of channels 1 channel (Ch.0)
Page 153: Input/Output Pins And External Connections
SDIn #SPISS0 SPICLKn #SPISS1 #SPISS #SPISS2 External SPI master device External SPI slave devices SPICLK SPICLK #SPISS SPICLK Figure 14.2.2.2 Connections between SPIA in Slave Mode and External SPI Master Device Seiko Epson Corporation 14-2 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 154: Pin Functions In Master Mode And Slave Mode
16-bit timer channel and converts it to the SPICLKn. The 16-bit timer must be run with an appro- priate reload data set. The SPICLKn frequency (baud rate) and the 16-bit timer reload data are calculated by the equations shown below. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 14-3 (Rev. 1.1)
Page 155: Clock Supply During Debugging
SDIn SDOn (Master mode) SDOn (Slave mode) SDOn (Slave mode) Writing data to the SPIA_nTXD register Figure 14.3.3.1 SPI Clock Phase and Polarity (SPIA_nMOD.LSBFST bit = 0, SPIA_nMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation 14-4 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 156: Data Format
6. Configure the DMA controller and set the following SPIA control bits when using DMA transfer: - Write 1 to the DMA transfer request enable bits in the SPIA_nTBEDMAEN and SPIA_nRBFDMAEN registers. (Enable DMA transfer requests) Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 14-5 (Rev. 1.1)
Page 157: Data Transmission In Master Mode
Data (W) → SPIA_nTXD Data (W) → SPIA_nTXD Software operations Data (W) → SPIA_nTXD 1 (W) → SPIA_nINTF.TENDIF Figure 14.5.2.1 Example of Data Sending Operations in Master Mode (SPIA_nMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation 14-6 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 158 Transfer destination SPIA_nTXD register address Control data dst_inc 0x3 (no increment) dst_size 0x1 (haflword) src_inc 0x1 (+2) src_size 0x1 (halfword) R_power 0x0 (arbitrated for every transfer) n_minus_1 Number of transfer data cycle_ctrl 0x1 (basic transfer) Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 14-7 (Rev. 1.1)
Page 159: Data Reception In Master Mode
Software operations SPIA_nRXD → Data (R) Data (W) → SPIA_nTXD SPIA_nRXD → Data (R) 1 (W) → SPIA_nINTF.TENDIF Figure 14.5.3.1 Example of Data Receiving Operations in Master Mode (SPIA_nMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation 14-8 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 160 Control data dst_inc 0x3 (no increment) dst_size 0x1 (haflword) src_inc 0x3 (no increment) src_size 0x1 (halfword) R_power 0x0 (arbitrated for every transfer) n_minus_1 Number of transfer data cycle_ctrl 0x1 (basic transfer) Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 14-9 (Rev. 1.1)
Page 161: Terminating Data Transfer In Master Mode
Writing transmit data is not a trigger to start data transfer. Therefore, it is not necessary to write dummy data to the transmit data buffer when performing data reception only. Seiko Epson Corporation 14-10 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 162: Terminating Data Transfer In Slave Mode
1. Wait for an end-of-transmission interrupt (SPIA_nINTF.TENDIF bit = 1). Or determine end of transfer via the received data. 2. Set the SPIA_nCTL.MODEN bit to 0 to disable the SPIA Ch.n operations. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 14-11 (Rev. 1.1)
Page 163: Interrupts
SPIA_nINTF.BSY SPIA_nMOD register CPOL bit CPHA bit SPICLKn SDOn SPICLKn SDOn SPIA_nINTF.TENDIF Writing data to the SPIA_nTXD register Figure 14.6.1 SPIA_nINTF.BSY and SPIA_nINTF.TENDIF Bit Set Timings (when SPIA_nMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation 14-12 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 164: Dma Transfer Requests
16 bits 15 bits 14 bits 13 bits 12 bits 11 bits 10 bits 9 bits 8 bits 7 bits 6 bits 5 bits 4 bits 3 bits 2 bits Setting prohibited Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 14-13 (Rev. 1.1)
Page 165: Spia Ch.n Control Register
Note: If the SPIA_nCTL.MODEN bit is altered from 1 to 0 while sending/receiving data, the data being sent/received cannot be guaranteed. When setting the SPIA_nCTL.MODEN bit to 1 again after that, be sure to write 1 to the SPIA_nCTL.SFTRST bit as well. Seiko Epson Corporation 14-14 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 166: Spia Ch.n Transmit Data Register
These bits indicate the SPIA interrupt cause occurrence status. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag (OEIF, TENDIF) 0 (W): Ineffective Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 14-15 (Rev. 1.1)
Page 167: Spia Ch.n Interrupt Enable Register
Ch.15) when a receive buffer full state has occurred. 1 (R/W): Enable DMA transfer request 0 (R/W): Disable DMA transfer request Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented chan- nels are ineffective. Seiko Epson Corporation 14-16 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 168: Quad Synchronous Serial Interface (Qspi)
• Can issue a DMA transfer request when a receive buffer full, a transmit buffer empty, or a memory mapped ac- cess (32-bit read) occurs. Figure 15.1.1 shows the QSPI configuration. Table 15.1.1 QSPI Channel Configuration of S1C31W74 Item S1C31W74 Number of channels 1 channel (Ch.0)
Page 169: Input/Output Pins And External Connections
In this case, GPIO pins other than #QSPISSn can also be used as the slave select output ports to connect the QSPI to more than one external QSPI device. Figures 15.2.2.1 to 15.2.2.7 show connection diagrams between the QSPI in each mode and external QSPI devices. Seiko Epson Corporation 15-2 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 170 External dual-I/O SPI slave devices QSDIOn0 SDIO0 QSPICLKn SPICK #SPISS SDIO1 SDIO0 SPICK Figure 15.2.2.3 Connections between QSPI in Register Access Master Mode and External Dual-I/O SPI Slave Devices Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 15-3 (Rev. 1.1)
Page 171 #SPISS2 External single-I/O SPI master device SPICK SPICK External single-I/O SPI slave devices #SPISS SPICK Figure 15.2.2.5 Connections between QSPI in Slave Mode and External Single-I/O SPI (Legacy SPI) Master Device Seiko Epson Corporation 15-4 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 172 QSDIO2 QSDIO2 QSDIO1 QSDIO1 QSDIO0 QSDIO0 QSPICLK QSPICLK External QSPI slave devices #QSPISS QSDIO3 QSDIO2 QSDIO1 QSDIO0 QSPICLK Figure 15.2.2.7 Connections between QSPI in Slave Mode and External QSPI Master Device Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 15-5 (Rev. 1.1)
Page 173: Pin Functions In Master Mode And Slave Mode
To supply CLK_QSPIn to the QSPI, the 16-bit timer clock source must be enabled in the clock generator. It does not matter how the T16_mCTL.MODEN and T16_mCTL.PRUN bits of the corresponding 16-bit timer channel are set (1 or 0). Seiko Epson Corporation 15-6 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 174: Clock Supply During Debugging
(Master mode, output) QSDIOn (Slave mode, output) QSDIOn (Slave mode, output) QSDIOn Writing data to the QSPI_nTXD register Figure 15.3.3.1 QSPI Clock Phase and Polarity (QSPI_nMOD.LSBFST bit = 0, QSPI_nMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 15-7 (Rev. 1.1)
Page 175: Data Format
Figure 15.4.2 Data Format Selection for Dual Transfer Mode Using the QSPI_nMOD.LSBFST Bit (QSPI_nMOD.TMOD[1:0] bits = 0x1, QSPI_nMOD.CHDL[3:0] bits = 0x7, QSPI_nMOD.CHLN[3:0] bits = 0x7, QSPI_nMOD.CPOL bit = 0, QSPI_nMOD.CPHA bit = 0) Seiko Epson Corporation 15-8 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 176: Operations
(QSPI_nCTL.DIR bit = 1). The number of data transfer clocks is configured with the QSPI_nMOD. CHLN[3:0] bits. Since four data lines are used for data transfer, the data bit length (number of clocks) is obtained by dividing the number of transfer data bits by four. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 15-9 (Rev. 1.1)
Page 177: Memory Mapped Access Mode
The QSPI treats the data cycle as 2 cycles including 2 driving cycles. (QSPI_nMOD.CHDL[3:0] bits = 0x1, QSPI_nMOD.CHLN[3:0] bits = 0x1) Figure 15.5.2.1 XIP Example - Spansion S25FL128S Quad I/O Read Command Sequence (3-byte address, 0xeb [ExtAdd = 0], LC = 0b00) Seiko Epson Corporation 15-10 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 178: Initialization
- QSPI_nMOD.NOCLKDIV bit (Select master mode operating clock) - QSPI_nMOD.LSBFST bit (Select MSB first/LSB first) - QSPI_nMOD.CPHA bit (Select clock phase) - QSPI_nMOD.CPOL bit (Select clock polarity) - QSPI_nMOD.MST bit (Select master/slave mode) Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 15-11 (Rev. 1.1)
Page 179: Data Transmission In Master Mode
Even if the clock is being output from the QSPICLKn pin, the next transmit data can be written to the QSPI_ nTXD register after making sure the QSPI_nINTF.TBEIF bit is set to 1. Seiko Epson Corporation 15-12 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 180 DMA transfer in advance so that transmit data will be transferred to the QSPI_nTXD register. For more information on DMA, refer to the “DMA Controller” chapter. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 15-13 (Rev. 1.1)
Page 181: Data Reception In Register Access Master Mode
TMOD[1:0] bits is received when the QSPI_nINTF.RBFIF bit is set to 1, the QSPI_nRXD register is overwritten with the newly received data and the previously received data is lost. In this case, the QSPI_nINTF.OEIF bit is set. Seiko Epson Corporation 15-14 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 182 DMA controller and dummy data is transferred from the specified memory to the QSPI_ nTXD register via DMA Ch.x when the QSPI_nINTF.TBEIF bit is set to 1 (transmit buffer empty). Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 15-15 (Rev. 1.1)
Page 183 DMA controller transfers data from the QSPI_nRXD register and then writes another dummy byte to the QSPI_nTXD register, allowing the QSPI to read the next data. 13. Wait for a DMA interrupt. Seiko Epson Corporation 15-16 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 184: Data Reception In Memory Mapped Access Mode
If the address in the memory mapped access area that is continuous to the previous read address is read when the FIFO contains the prefetched data (FIFO data ready status), the prefetched data is sent to the internal system bus with the HREADY signal held high (zero-wait read). Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 15-17 (Rev. 1.1)
Page 185 Data cycle 3 QSPI_nMOD register Dummy cycle Data cycle 1 (prefetching) (prefetching) CPOL bit CPHA bit QSPICLKn QSDIOn[3:0] Figure 15.5.6.1 Data Receiving Operation in Memory Mapped Access Mode - First 32-bit Read Seiko Epson Corporation 15-18 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 186 HRDATA fifo_read_level Data cycle Data cycle QSPI_nMOD register (for n+8) (prefetching) CPOL bit CPHA bit QSPICLKn QSDIOn[3:0] Figure 15.5.6.2 Data Receiving Operation in Memory Mapped Access Mode - 32-bit Sequential Read Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 15-19 (Rev. 1.1)
Page 187 Dummy cycle (low-order 16 bits) (for n) (for n+8) QSPI_nMOD register #QSPISSn CPOL bit CPHA bit QSPICLKn QSDIOn[3:0] Figure 15.5.6.3 Data Receiving Operation in Memory Mapped Access Mode - 32-bit Non-Sequential Read Seiko Epson Corporation 15-20 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 188 HADDR HTRANS HSIZE HREADY HRDATA QSPI_nMOD register Dummy cycle Data cycle CPOL bit CPHA bit QSPICLKn QSDIOn[3:0] Figure 15.5.6.4 Data Receiving Operation in Memory Mapped Access Mode - First 8/16-bit Read Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 15-21 (Rev. 1.1)
Page 189 HCLK HSEL HADDR HTRANS HSIZE HREADY HRDATA QSPI_nMOD register Data cycle CPOL bit CPHA bit QSPICLKn QSDIOn[3:0] Figure 15.5.6.5 Data Receiving Operation in Memory Mapped Access Mode - 8/16-bit Sequential Read Seiko Epson Corporation 15-22 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 190 Address cycle Dummy cycle Data cycle (low-order 16 bits) QSPI_nMOD register #QSPISSn CPOL bit CPHA bit QSPICLKn QSDIOn[3:0] Figure 15.5.6.6 Data Receiving Operation in Memory Mapped Access Mode - 8/16-bit Non-Sequential Read Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 15-23 (Rev. 1.1)
Page 191 The transfer source/destination and control data must be set for the DMA controller and the relevant DMA channel must be enabled to start a DMA transfer in advance. For more information on DMA, refer to the “DMA Controller” chapter. Seiko Epson Corporation 15-24 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 192: Terminating Memory Mapped Access Operations
1. Wait for an end-of-transmission interrupt (QSPI_nINTF.TENDIF bit = 1). 2. Set the QSPI_nCTL.MODEN bit to 0 to disable the QSPI Ch.n operations. 3. Stop the 16-bit timer to disable the clock supply to QSPI Ch.n. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 15-25 (Rev. 1.1)
Page 193: Data Transfer In Slave Mode
Data (W) → QSPI_nTXD Software operations QSPI_nRXD → Data (R) QSPI_nRXD → Data (R) Figure 15.5.9.1 Example of Data Transfer Operations in Slave Mode (QSPI_nMOD.CHDL[3:0] bits = QSPI_nMOD.CHLN[3:0] bits = 0x3) Seiko Epson Corporation 15-26 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 194: Terminating Data Transfer In Slave Mode
The QSPI_nINTF register also contains the BSY and MMABSY bits that indicate the QSPI operating status in reg- ister access and memory mapped access modes, respectively. Figure 15.6.1 shows the QSPI_nINTF.BSY, QSPI_ nINTF.MMABSY and QSPI_nINTF.TENDIF bit set timings. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 15-27 (Rev. 1.1)
Page 195: Dma Transfer Requests
When a 32-bit data is prefetched into the FIFO When the FIFO read access FIFO data FIFO data ready flag in memory mapped access mode level is cleared to 0 ready (internal signal) Seiko Epson Corporation 15-28 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 196: Control Registers
Note: When using the QSPI in slave mode, the QSPI_nMOD.CHDL[3:0] bits should be set to the same value as the QSPI_nMOD.CHLN[3:0] bits. Bits 11–8 CHLN[3:0] These bits set the number of clocks for data transfer. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 15-29 (Rev. 1.1)
Page 197 0 (R/W): MSB first Bit 2 CPHA Bit 1 CPOL These bits set the QSPI clock phase and polarity. For more information, refer to “QSPI Clock (QSPI- CLKn) Phase and Polarity.” Seiko Epson Corporation 15-30 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 198: Qspi Ch.n Control Register
Note: If the QSPI_nCTL.MODEN bit is altered from 1 to 0 while sending/receiving data, the data being sent/received cannot be guaranteed. When setting the QSPI_nCTL.MODEN bit to 1 again after that, be sure to write 1 to the QSPI_nCTL.SFTRST bit as well. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 15-31 (Rev. 1.1)
Page 199: Qspi Ch.n Transmit Data Register
Transmit/receive busy 0 (R): Idle Bit 6 MMABSY This bit indicates the QSPI memory mapped access operating status. 1 (R): Memory mapped access state machine busy 0 (R): Idle Bits 5–4 Reserved Seiko Epson Corporation 15-32 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 200: Qspi Ch.n Interrupt Enable Register
Ch.15) when a transmit buffer empty state has occurred. 1 (R/W): Enable DMA transfer request 0 (R/W): Disable DMA transfer request Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented chan- nels are ineffective. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 15-33 (Rev. 1.1)
Page 201: Qspi Ch.n Receive Buffer Full Dma Request Enable Register
11 clocks 10 clocks 9 clocks 8 clocks 7 clocks 6 clocks 5 clocks 4 clocks 3 clocks 2 clocks 1 clock Note: These bits specify a number of system clocks. Seiko Epson Corporation 15-34 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 202: Qspi Ch.n Remapping Start Address High Register
Flash memory in the memory mapped access mode. This setting is re- quired to output the XIP confirmation bit to Micron Flash memories or to output the mode byte to Spansion Flash memories. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 15-35 (Rev. 1.1)
Page 203 The QSDIOn[3:0] pins are used. Dual transfer mode The QSDIOn[1:0] pins are used. The QSDIOn[3:2] pins are not used. Single transfer mode The QSDIOn[1:0] pins are used. The QSDIOn[3:2] pins are not used. Seiko Epson Corporation 15-36 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 204: Qspi Ch.n Mode Byte Register
Note: In memory mapped access mode, the mode byte is always output from the LSB first. When us- ing a Flash memory that expects the mode byte to be output from the MSB first, write the mode byte to this register in reverse bit order. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 15-37 (Rev. 1.1)
Page 205: C (I2C)
• The input filter for the SDA and SCL inputs does not comply with the standard for removing noise spikes less than 50 ns. Figure 16.1.1 shows the I2C configuration. Table 16.1.1 I2C Channel Configuration of S1C31W74 Item S1C31W74 Number of channels 2 channels (Ch.0 and Ch.1)
Page 206: Input/Output Pins And External Connections
• The internal pull-up resistors for the I/O ports cannot be used for pulling up SDA and SCL. • When the I2C is set into master mode, no other master device can be connected to the I bus. Seiko Epson Corporation 16-2 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 207: Clock Settings
16.3.3.1). Note: The I C bus transfer rate is limited to 100 kbit/s in standard mode or 400 kbit/s in fast mode. Do not set a transfer rate exceeding the limit. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 16-3 (Rev. 1.1)
Page 208: Operations
- Set the I2C_nCTL.MST bit to 0. (Set slave mode) - Set the I2C_nCTL.SFTRST bit to 1. (Execute software reset) - Set the I2C_nCTL.MODEN bit to 1. (Enable I2C Ch.n operations) Seiko Epson Corporation 16-4 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 209: Data Transmission In Master Mode
I2C_nINTF.NACKIF bit = 1 (NACK received), the I2C Ch.n generates a repeated START condi- tion. When the repeated START condition has been generated, the I2C_nINTF.STARTIF and I2C_nINTF. TBEIF bits are both set to 1 same as when a START condition has been generated. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 16-5 (Rev. 1.1)
Page 210 Last data sent? Retry? Write 1 to the I2C_nCTL.TXSTOP bit Write data to the I2C_nTXD register Wait for an interrupt request (I2C_nINTF.STOPIF = 1) Figure 16.4.2.2 Master Mode Data Transmission Flowchart Seiko Epson Corporation 16-6 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 211: Data Reception In Master Mode
10. (When DMA is not used) Repeat Steps 6 to 8 until the end of data reception. 11. Wait for a STOP condition interrupt (I2C_nINTF.STOPIF bit = 1). Clear the I2C_nINTF.STOPIF bit by writing 1 after the interrupt has occurred. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 16-7 (Rev. 1.1)
Page 212 S: START condition, Sr: Repeated START condition, P: STOP condition, A: ACK, A: NACK, Saddr/R: Slave address + R(1), Data n: 8-bit data Figure 16.4.3.1 Example of Data Receiving Operations in Master Mode Seiko Epson Corporation 16-8 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 213 Transfer destination Memory address to which the last received data is stored Control data dst_inc 0x0 (+1) dst_size 0x0 (byte) src_inc 0x3 (no increment) src_size 0x0 (byte) R_power 0x0 (arbitrated for every transfer) n_minus_1 Number of receive data cycle_ctrl 0x1 (basic transfer) Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 16-9 (Rev. 1.1)
Page 214: 10-Bit Addressing In Master Mode
Clear the I2C_nINTF.STARTIF bit by writing 1 after the interrupt has occurred. 9. Write the first address to the I2C_nTXD.TXD[7:1] bits and 1 that represents READ as the data transfer di- rection to the I2C_nTXD.TXD0 bit. 10. Perform data reception. Seiko Epson Corporation 16-10 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 215: Data Transmission In Slave Mode
Go to Step 6 when a STOP condition interrupt has occurred. ii. Go to Step 2 when a START condition interrupt has occurred. 6. Clear the I2C_nINTF.STOPIF bit and then terminate data sending operations. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 16-11 (Rev. 1.1)
Page 216 A: ACK, A: NACK, Saddr/R: Slave address + R(1), Saddr/W: Slave address + W(0), STARTIF = 1 Data n: 8-bit data Figure 16.4.5.1 Example of Data Sending Operations in Slave Mode Seiko Epson Corporation 16-12 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 217: Data Reception In Slave Mode
I2C Ch.n sends an ACK and pulls down SCL to low. The received data in the shift register is transferred to the receive data buffer and the I2C_nINTF.RBFIF and I2C_nINTF.BYTEENDIF bits are both set to 1. After that, the received data can be read out from the I2C_nRXD register. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 16-13 (Rev. 1.1)
Page 218 Wait for an interrupt request (I2C_nINTF.RBFIF = 1) Last data received next? Write 1 to the I2C_nCTL.TXNACK bit Read receive data from the I2C_nRXD register Last data received? Figure 16.4.6.2 Slave Mode Data Reception Flowchart Seiko Epson Corporation 16-14 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 219: Slave Operations In 10-Bit Address Mode
If SDA does not change from low when the I2C Ch.n outputs the ninth clock, it is regarded as an automatic bus clearing failure. In this case, the I2C Ch.n clears the I2C_nCTL.TXSTART bit to 0 and sets both the I2C_nINTF. ERRIF and I2C_nINTF.STARTIF bits to 1. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 16-15 (Rev. 1.1)
Page 220: Error Detection
4 <Master mode only> When 1 is written to the I2C_nCTL. I2C_nINTF.ERRIF = 1 TXSTART bit while the I2C_nINTF.BSY bit = 0 (Refer to “Au- Automatic bus clearing I2C_nCTL.TXSTART = 0 tomatic Bus Clearing Operation.”) failure I2C_nINTF.STARTIF = 1 Seiko Epson Corporation 16-16 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 221: Interrupts
Master mode BRT + 3 CLK_I2Cn TXSTART = 1 TXSTART = 0 STARTIF = 1 Slave mode Address matching the I2C_nOADR register BSY = 1 TR = 0/1 STARTIF = 1 Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 16-17 (Rev. 1.1)
Page 222: Dma Transfer Requests
16.7 Control Registers I2C Ch.n Clock Control Register Register name Bit name Initial Reset Remarks I2C_nCLK 15–9 – 0x00 – – DBRUN 7–6 – – 5–4 CLKDIV[1:0] 3–2 – – 1–0 CLKSRC[1:0] Seiko Epson Corporation 16-18 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 223: I2C Ch.n Mode Register
Note: The I2C_nMOD register settings can be altered only when the I2C_nCTL.MODEN bit = 0. I2C Ch.n Baud-Rate Register Register name Bit name Initial Reset Remarks I2C_nBR 15–8 – 0x00 – – – – 6–0 BRT[6:0] 0x7f Bits 15–7 Reserved Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 16-19 (Rev. 1.1)
Page 224: I2C Ch.n Own Address Register
STOP condition has been generated. This bit is automatically cleared when the bus free time (t defined in the I C Specifications) has elapsed after the STOP condition has been generated. Seiko Epson Corporation 16-20 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 225: I2C Ch.n Transmit Data Register
Register name Bit name Initial Reset Remarks I2C_nRXD 15–8 – 0x00 – – 7–0 RXD[7:0] 0x00 Bits 15–8 Reserved Bits 7–0 RXD[7:0] The receive data buffer can be read through these bits. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 16-21 (Rev. 1.1)
Page 226: I2C Ch.n Status And Interrupt Flag Register
Bit 0 TBEIF These bits indicate the I2C interrupt cause occurrence status. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective Seiko Epson Corporation 16-22 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 227: I2C Ch.n Interrupt Enable Register
I2C_nINTE.NACKIE bit: NACK reception interrupt I2C_nINTE.STOPIE bit: STOP condition interrupt I2C_nINTE.STARTIE bit: START condition interrupt I2C_nINTE.ERRIE bit: Error detection interrupt I2C_nINTE.RBFIE bit: Receive buffer full interrupt I2C_nINTE.TBEIE bit: Transmit buffer empty interrupt Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 16-23 (Rev. 1.1)
Page 228: I2C Ch.n Transmit Buffer Empty Dma Request Enable Register
(Ch.0–Ch.15) when a receive buffer full state has occurred. 1 (R/W): Enable DMA transfer request 0 (R/W): Disable DMA transfer request Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented chan- nels are ineffective. Seiko Epson Corporation 16-24 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 229: 16-Bit Pwm Timers (T16B)
- The capture circuit captures counter values using external/software trigger signals and generates interrupts or DMA requests. (Can be used to measure external event periods/cycles.) Figure 17.1.1 shows the T16B configuration. Table 17.1.1 T16B Channel Configuration of S1C31W74 Item S1C31W74 Number of channels 2 channels (Ch.0 and Ch.1)
Page 230: Input/Output Pins
If the port is shared with the T16B pin and other functions, the T16B input/output function must be assigned to the port before activating T16B. For more information, refer to the “I/O Ports” chapter. Seiko Epson Corporation 17-2 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 231: Clock Settings
Figure 17.3.4.1 Count Timing (During Count Up Operation) Note: When running the counter using the event counter clock, two dummy clocks must be input be- fore the first counting up/down can be performed. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 17-3 (Rev. 1.1)
Page 232: Operations
5. Set the following bits when using the interrupt: - Write 1 to the interrupt flags in the T16B_nINTF register. (Clear interrupt flags) - Set the interrupt enable bits in the T16B_nINTE register to 1. (Enable interrupts) Seiko Epson Corporation 17-4 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 233: Counter Block Operations
T16Bn, one of the operations shown below is required to read correctly by the CPU. - Read the counter value twice or more and check to see if the same value is read. - Stop the timer and then read the counter value. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 17-5 (Rev. 1.1)
Page 234 0x0000 and continues counting down from the new MAX value after a counter under- flow occurs. In one-shot down count mode, the counter returns to the MAX value if a counter underflow occurs and stops automatically at that point. Seiko Epson Corporation 17-6 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 235 0x0000 and then starts counting up to the new MAX val- In one-shot up/down count mode, the counter stops automatically when it reaches 0x0000 during count down operation. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 17-7 (Rev. 1.1)
Page 236: Comparator/Capture Block Operations
When the counter reaches the MAX value in comparator mode, the T16B_nINTF.CNTMAXIF bit (counter MAX interrupt flag) is set to 1. When the counter reaches 0x0000, the T16B_nINTF.CNTZEROIF bit (counter zero interrupt flag) is set to 1. Seiko Epson Corporation 17-8 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 237 Count cycle = — — — — — — — — [s] (Eq. 17.2) CLK_T16B CLK_T16B Where T16B_nCCRm register setting value (0 to 65,535) MAX: T16B_nMC register setting value (0 to 65,535) : Count clock frequency [Hz] CLK_T16B Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 17-9 (Rev. 1.1)
Page 238 (T16B_nMC register) Compare period Compare buffer Counter value Time 0x0000 CNTMAXIF = 1 CNTMAXIF = 1 CNTMAXIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation 17-10 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 239 Count cycle MAX value (T16B_nMC register) Compare period Compare buffer Counter value Time 0x0000 CNTMAXIF = 1 CNTMAXIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 17-11 (Rev. 1.1)
Page 240 Compare buffer value Compare period Time 0x0000 CNTZEROIF = 1 CNTZEROIF = 1 CNTZEROIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation 17-12 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 241 Time 0x0000 CNTMAXIF = 1 CNTZEROIF = 1 CNTMAXIF = 1 CNTZEROIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 17-13 (Rev. 1.1)
Page 242 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 (Note that the T16B_nINTF.CMPCAPmIF/CNTMAXIF/CNTZEROIF bit clearing operations via software are omitted from the figure.) Figure 17.4.3.2 Compare Buffer Operations Seiko Epson Corporation 17-14 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 243 If the captured data stored in the T16B_nCCRm register is overwritten by the next trigger when the T16B_ nINTF.CMPCAPmIF bit is still set, an overwrite error occurs (the T16B_nINTF.CAPOWmIF bit is set). Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 17-15 (Rev. 1.1)
Page 244 Capture trigger signal T16B_nCCRm.CC[15:0] Capturing operation (2) Asynchronous capture mode (When T16B_nCCCTLm.CAPTRG[1:0] bits = 0x3) Count clock T16B_nTC.TC[15:0] Capture trigger signal T16B_nCCRm.CC[15:0] Capturing operation Figure 17.4.3.4 Synchronous Capture Mode/Asynchronous Capture Mode Seiko Epson Corporation 17-16 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 245: Tout Output Control
Furthermore, when the T16B_nCCCTLm.TOUTMT bit is set to 1, the TOUT circuit uses the MATCH signal output from another system in the circuit pair (0 and 1, 2 and 3, 4 and 5). This makes it possible to change the signal twice within a counter cycle. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 17-17 (Rev. 1.1)
Page 246 Software control mode (0x0) Set mode (0x1) Toggle/reset mode (0x2) Set/reset mode (0x3) Toggle mode(0x4) Reset mode (0x5) Toggle/set mode (0x6) Reset/set mode (0x7) ∗ ( ) indicates the T16B_nCCCTLm.TOUTMD[2:0] bit-setting value. Seiko Epson Corporation 17-18 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 247 Set/reset mode (0x3) Toggle mode(0x4) Reset mode (0x5) Toggle/set mode (0x6) Reset/set mode (0x7) ∗ ( ) indicates the T16B_nCCCTLm.TOUTMD[2:0] bit-setting value. Figure 17.4.4.2 TOUT Output Waveform (T16B_nCCCTLm.TOUTMT bit = 0) Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 17-19 (Rev. 1.1)
Page 248 Set/reset mode (0x3) TOUTn0 TOUTn1 Toggle mode(0x4) TOUTn0 TOUTn1 Reset mode (0x5) TOUTn0 TOUTn1 Toggle/set mode (0x6) TOUTn0 TOUTn1 Reset/set mode (0x7) TOUTn0 TOUTn1 ∗ ( ) indicates the T16B_nCCCTLm.TOUTMD[2:0] bit-setting value. Seiko Epson Corporation 17-20 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 249 Set/reset mode (0x3) TOUTn0 TOUTn1 Toggle mode(0x4) TOUTn0 TOUTn1 Reset mode (0x5) TOUTn0 TOUTn1 Toggle/set mode (0x6) TOUTn0 TOUTn1 Reset/set mode (0x7) TOUTn0 TOUTn1 ∗ ( ) indicates the T16B_nCCCTLm.TOUTMD[2:0] bit-setting value. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 17-21 (Rev. 1.1)
Page 250 Toggle/set mode (0x6) TOUTn0 TOUTn1 Reset/set mode (0x7) TOUTn0 TOUTn1 ∗ ( ) indicates the T16B_nCCCTLm.TOUTMD[2:0] bit-setting value. Figure 17.4.4.3 TOUT Output Waveform (T16B_nCCCTL0.TOUTMT bit = 1, T16B_nCCCTL1.TOUTMT bit = 0) Seiko Epson Corporation 17-22 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 251: Interrupt
Bit 8 DBRUN This bit sets whether the T16B Ch.n operating clock is supplied during debugging or not. 1 (R/W): Clock supplied during debugging 0 (R/W): No clock supplied during debugging Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 17-23 (Rev. 1.1)
Page 252: T16B Ch.n Counter Control Register
T16B_nCTL.ONEST bit setting (see Table 17.7.2). Bit 3 ONEST This bit selects the counter repeat/one-shot mode. The count mode is configured with this selection and the T16B_nCTL.CNTMD[1:0] bit settings (see Table 17.7.2). Seiko Epson Corporation 17-24 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 253: T16B Ch.n Max Counter Data Register
T16B_nCTL.MODEN bit to 1 until the T16B_nCS.BSY bit is set to 0 from 1. • Do not set the T16B_nMC.MC[15:0] bits to 0x0000. T16B Ch.n Timer Counter Data Register Register name Bit name Initial Reset Remarks T16B_nTC 15–0 TC[15:0] 0x0000 – Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 17-25 (Rev. 1.1)
Page 254: T16B Ch.n Counter Status Register
This bit indicates the currently set count direction. 1 (R): Count up 0 (R): Count down Bit 0 This bit indicates the counter operating status. 1 (R): Running 0 (R): Idle Seiko Epson Corporation 17-26 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 255: T16B Ch.n Interrupt Flag Register
Note: The configuration of the T16B_nINTF.CAPOWmIF and T16B_nINTF.CMPCAPmIF bits depends on the model. The bits corresponding to the comparator/capture circuits that do not exist are read-only bits and are always fixed at 0. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 17-27 (Rev. 1.1)
Page 256: T16B Ch.n Interrupt Enable Register
The bits corresponding to the comparator/capture circuits that do not exist are read-only bits and are always fixed at 0. • To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared before enabling interrupts. Seiko Epson Corporation 17-28 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 257: T16B Ch.n Comparator/Capture M Control Register
These bits select the trigger edge(s) of the trigger signal at which the counter value is captured in the T16B_nCCRm register in capture mode (see Table 17.7.4). The T16B_nCCCTLm.CAPTRG[1:0] bits are control bits for capture mode and are ineffective in comparator mode. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 17-29 (Rev. 1.1)
Page 258 T h e s i g n a l b e c o m e s i n a c t i v e b y t h e M AT C H m o r MATCHm+1 signal. TOUTnm+1 The signal becomes inactive by the MATCHm+1 or MATCHm signal. Seiko Epson Corporation 17-30 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 259: T16B Ch.n Compare/Capture M Data Register
In capture mode, this register is configured as the capture register and the counter value captured by the capture trigger signal is loaded. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 17-31 (Rev. 1.1)
Page 260: T16B Ch.n Counter Max/Zero Dma Request Enable Register
(Ch.0–Ch.15) when the counter value reaches the compare data or is captured. 1 (R/W): Enable DMA transfer request 0 (R/W): Disable DMA transfer request Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented chan- nels are ineffective. Seiko Epson Corporation 17-32 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 261: Sound Generator (Snda)
Sound register MOSEL[1:0] Sound generation STIM[3:0] circuit BZOUT SINV Output control circuit SSTP #BZOUT Interrupt control circuit EMIE EMIF EDIE EDIF DMA request controller control circuit EMDMAENx Figure 18.1.1 SNDA Configuration Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 18-1 (Rev. 1.1)
Page 262: Output Pins And External Connections
Piezoelectric buzzer #BZOUT S1C31 SNDA Figure 18.2.2.1 Connection between SNDA and Piezoelectric Buzzer (Direct Drive) Piezoelectric buzzer BZOUT S1C31 SNDA Figure 18.2.2.2 Connection between SNDA and Piezoelectric Buzzer (Single Pin Drive) Seiko Epson Corporation 18-2 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 263: Clock Settings
Normal buzzer mode generates a buzzer signal with the software specified frequency and duty ratio, and outputs the generated signal to outside the IC. The buzzer output duration can also be controlled via software. An output start/stop procedure and the SNDA operations are shown below. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 18-3 (Rev. 1.1)
Page 264 Buzzer signal frequency [Hz] BZOUT DUTY: Buzzer signal duty ratio [%] However, the following settings are prohibited: • Settings as SNDADAT.SFRQ[7:0] bits ≤ SNDADAT.SLEN[5:0] bits • Settings as SNDADAT.SFRQ[7:0] bits = 0x00 Seiko Epson Corporation 18-4 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 265 – 71.9 35.9 0x15 – – – – 68.8 34.4 0x14 – – – – 65.6 32.8 0x13 – – – – 62.5 31.3 0x12 – – – – 59.4 29.7 Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 18-5 (Rev. 1.1)
Page 266: Buzzer Output In One-Shot Buzzer Mode
At the same time, the SNDAINTF.EDIF bit (sound output completion interrupt flag) is set to 1 and the SNDAINTF.SBSY bit is cleared to 0. Figure 18.4.3.1 shows a buzzer output timing chart in one-shot buzzer mode. Seiko Epson Corporation 18-6 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 267: Output In Melody Mode
At the same time, the SNDAINTF.EDIF bit (sound output completion interrupt flag) is set to 1 and the SNDAINTF.SBSY bit is cleared to 0. Figure 18.4.4.1 shows a melody mode operation timing chart. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 18-7 (Rev. 1.1)
Page 268 Dotted quarter rest 0x07 Quarter note Quarter rest 0x05 Dotted eighth note Dotted eighth rest 0x03 Eighth note Eighth rest 0x01 Sixteenth note Sixteenth rest 0x00 Thirty-second note Thirty-second rest Other Setting prohibited Seiko Epson Corporation 18-8 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 269: Interrupts
1 is register written to the SNDACTL.SSTP bit Sound output SNDAINTF.EDIF When a sound output has completed Writing 1 or writing to completion the SNDADAT register Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 18-9 (Rev. 1.1)
Page 270: Dma Transfer Requests
Bit 7 Reserved Bits 6–4 CLKDIV[2:0] These bits select the division ratio of the SNDA operating clock. Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the clock source of SNDA. Seiko Epson Corporation 18-10 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 271: Snda Select Register
This bit selects an output pin drive mode. 1 (R/W): Normal drive mode 0 (R/W): Direct drive mode For more information, refer to “Output Pin Drive Mode.” Bits 1–0 MOSEL[1:0] These bits select a sound output mode. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 18-11 (Rev. 1.1)
Page 272: Snda Control Register
0 (R/W): Note When a rest is selected, the BZOUT pin goes low and the #BZOUT pin goes high during the output duration. This bit is ignored in normal buzzer mode/one-shot buzzer mode. Seiko Epson Corporation 18-12 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 273: Snda Interrupt Flag Register
0x00 – – 7–2 – 0x00 – EMIE EDIE Bits 15–2 Reserved Bit 1 EMIE Bit 0 EDIE These bits enable SNDA interrupts. 1 (R/W): Enable interrupts 0 (R/W): Disable interrupts Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 18-13 (Rev. 1.1)
Page 274: Snda Sound Buffer Empty Dma Request Enable Register
(Ch.0–Ch.15) when a sound buffer empty state has occurred. 1 (R/W): Enable DMA transfer request 0 (R/W): Disable DMA transfer request Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented chan- nels are ineffective. Seiko Epson Corporation 18-14 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 275: Ir Remote Controller (Remc2)
• Automatic data setting function for continuous data transmission. • Output signal inverting function supporting various formats. • EL lamp drive waveform can be generated for an application example. Figure 19.1.1 shows the REMC2 configuration. Table 19.1.1 REMC2 Channel Configuration of S1C31W74 Item S1C31W74 Number of channels...
Page 276: External Connections
2. Configure the REMC2CLK.CLKSRC[1:0] and REMC2CLK.CLKDIV[3:0] bits. (Configure operating clock) 3. Assign the REMC2 output function to the port. (Refer to the “I/O Ports” chapter.) 4. Configure the following REMC2DBCTL register bits: Seiko Epson Corporation 19-2 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 277: Data Transmission Procedures
The REMC2 outputs the logical AND between the carrier signal output from the carrier generator and the data sig- nal output from the data signal generator. Figure 19.4.3.1 shows an example of the output waveform. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 19-3 (Rev. 1.1)
Page 278 The data signal is generated by comparing the values of the 16-bit counter for data signal generation (REMC2DBCNT.DBCNT[15:0] bits) that runs with CLK_REMC2 and the setting values of the REMC2A- PLEN.APLEN[15:0] and REMC2DBLEN.DBLEN[15:0] bits. Figure 19.4.3.3 shows an example of the data signal generated. Seiko Epson Corporation 19-4 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 279: Continuous Data Transmission And Compare Buffers
(REMC2DBCTL.TRMD bit = 1), the counter stops automatically when the counter value is matched with the REMC2DBLEN.DBLEN[15:0] bit-setting value. 19.4.4 Continuous Data Transmission and Compare Buffers Figure 19.4.4.1 shows an operation example of continuous data transmission with the compare buffer enabled. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 19-5 (Rev. 1.1)
Page 280: Interrupts
The REMC2 provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the CPU only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For more information on interrupt control, refer to the “Interrupt” chapter. Seiko Epson Corporation 19-6 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 281: Application Example: Driving El Lamp
This bit sets whether the REMC2 operating clock is supplied during debugging or not. 1 (R/W): Clock supplied during debugging 0 (R/W): No clock supplied during debugging Bits 7–4 CLKDIV[3:0] These bits select the division ratio of the REMC2 operating clock. Bits 3–2 Reserved Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 19-7 (Rev. 1.1)
Page 282: Remc2 Data Bit Counter Control Register
This bit starts/stops counting by the internal counters (16-bit counter for data signal generation and 8-bit counter for carrier generation). 1 (W): Start counting 0 (W): Stop counting 1 (R): Counting 0 (R): Idle Seiko Epson Corporation 19-8 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 283: Remc2 Data Bit Counter Register
0x0000 H0/S0 Cleared by writing 1 to the REMC2DBCTL.REMCRST bit. Bits 15–0 DBCNT[15:0] The current value of the 16-bit counter for data signal generation can be read out through these bits. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 19-9 (Rev. 1.1)
Page 284: Remc2 Data Bit Active Pulse Length Register
Transfer to the REMC2APLEN buffer has not completed. 0 (R): Transfer to the REMC2APLEN buffer has completed. While this bit is set to 1, writing to the REMC2APLEN.APLEN[15:0] bits is ineffective. Seiko Epson Corporation 19-10 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 285: Remc2 Interrupt Enable Register
REMC2CARR.CRPER[7:0] bit-setting value. (See Figure 19.4.3.2.) REMC2 Carrier Modulation Control Register Register name Bit name Initial Reset Remarks REMC2CCTL 15–8 – 0x00 – – 7–1 – 0x00 – CARREN Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 19-11 (Rev. 1.1)
Page 286 This bit enables carrier modulation. 1 (R/W): Enable carrier modulation 0 (R/W): Disable carrier modulation (output data signal only) Note: When carrier modulation is disabled, the REMC2DBCTL.REMOINV bit should be set to 0. Seiko Epson Corporation 19-12 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 287: Lcd Driver (Lcd32B)
• Includes a power supply for 1/4 or 1/5 bias driving (allows external voltages to be applied). • Provides the frame signal monitoring output pin. • Can generate interrupts every frame. Figure 20.1.1 shows the LCD32B configuration. Table 20.1.1 LCD32B Configuration of S1C31W74 Item S1C31W74 Number of segments supported Max.
Page 288: Output Pins And External Connections
Note: When the panel is connected, the LCD32BCTL.LCDDIS bit must be set to 1 to bias the panel even if display is turned off. COMm LCD Panel COM0 SEGn SEG0 S1C31 LCD32B Figure 20.2.2.1 Connections between LCD32B and an LCD Panel Seiko Epson Corporation 20-2 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 289: Clock Settings
39.4 52.5 78.8 157.5 0x18 20.5 23.4 27.3 32.8 41.0 54.6 81.9 163.8 0x17 21.3 24.4 28.4 34.1 42.7 56.9 85.3 170.7 0x16 22.3 25.4 29.7 35.6 44.5 59.4 89.0 178.1 Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 20-3 (Rev. 1.1)
Page 290 85.3 93.1 102.4 113.8 0x02 85.3 91.0 97.5 105.0 113.8 124.1 136.5 151.7 0x01 128.0 136.5 146.3 157.5 170.7 186.2 204.8 227.6 0x00 256.0 273.1 292.6 315.1 341.3 372.4 409.6 455.1 Seiko Epson Corporation 20-4 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 291 12.2 12.6 13.1 13.7 0x0a 11.6 12.0 12.4 12.8 13.3 13.8 14.3 14.9 0x09 12.8 13.2 13.7 14.1 14.6 15.2 15.8 16.4 0x08 14.2 14.7 15.2 15.7 16.3 16.9 17.5 18.2 Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 20-5 (Rev. 1.1)
Page 292: Lcd Power Supply
LCD32BPWR.EXVCSEL bit to 1 and set both the LCD32BPWR.VCEN and LCD32BPWR.BSTEN bits to 0 to turn both the LCD voltage regulator and LCD voltage booster off. Figure 20.4.2.1 shows an external connection example for external voltage application mode. Seiko Epson Corporation 20-6 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 293: Lcd Voltage Regulator Settings
- Write 1 to the LCD32BCTL.LCDDIS bit. (Enable LCD driver pin discharge at display off) 4. Configure the following LCD32BTIM1 register bits: - LCD32BTIM1.LDUTY[4:0] bits (Set drive duty) - LCD32BTIM1.FRMCNT[4:0] bits (Set frame frequency) Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 20-7 (Rev. 1.1)
Page 294: Display On/Off
Drive duty can be set to 1/32 to 1/2 or static drive using the LCD32BTIM1.LDUTY[4:0] bits. Table 20.5.4.1 shows the correspondence between the LCD32BTIM1.LDUTY[4:0] bit settings, drive duty, and maximum number of dis- play segments. Seiko Epson Corporation 20-8 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 295 COM18 COM18 SEG86/COM17 SEG86 COM17 COM17 SEG87/COM16 SEG87 COM16 COM16 *1 The COM pins to be used depend on the drive duty selection. For more information, refer to “Drive Duty Switching.” Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 20-9 (Rev. 1.1)
Page 296: Drive Waveforms
COM0 COM0 COM1 COM2 COM3 COM4 COM5 COM1 COM6 COM24 COM25 COM26 COM28 COM2 COM29 COM30 COM31 SEGx COM30 COM31 SEGx Figure 20.5.5.1 1/32 Duty Drive Waveform (1/5 bias) Seiko Epson Corporation 20-10 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 297 COM29 COM30 COM31 (= V SEGx COM30 (= V COM31 (= V (= V (= V SEGx (= V (= V (= V Figure 20.5.5.2 1/32 Duty Drive Waveform (1/4 bias) Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 20-11 (Rev. 1.1)
Page 298 COM0 COM0 COM1 COM2 COM3 COM4 COM5 COM1 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM2 COM13 COM14 COM15 SEGx COM14 COM15 SEGx Figure 20.5.5.3 1/16 Duty Drive Waveform (1/5 bias) Seiko Epson Corporation 20-12 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 299 COM13 COM14 COM15 (= V SEGx COM14 (= V COM15 (= V (= V (= V SEGx (= V (= V (= V Figure 20.5.5.4 1/16 Duty Drive Waveform (1/4 bias) Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 20-13 (Rev. 1.1)
Page 300 20 LCD DRIVER (LCD32B) 1 frame LFRO display status COM0 COM0 COM1 COM2 COM3 COM4 COM5 COM1 COM6 COM7 SEGx COM2 COM6 COM7 SEGx Figure 20.5.5.5 1/8 Duty Drive Waveform (1/5 bias) Seiko Epson Corporation 20-14 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 301 SEGx (= V COM2 (= V COM6 (= V COM7 (= V (= V (= V SEGx (= V (= V (= V Figure 20.5.5.6 1/8 Duty Drive Waveform (1/4 bias) Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 20-15 (Rev. 1.1)
Page 302: Partial Common Output Drive
Note that using the n-line inverse AC drive function increases current consumption. Table 20.5.7.1 Selecting Number of Inverse Lines LCD32BTIM2.NLINE[4:0] bits Number of inverse lines 0x1f 31 lines 0x1e 30 lines 0x01 1 line 0x00 Normal drive Seiko Epson Corporation 20-16 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 303: Display Data Ram
When the LCD32BDSP.COMREV bit is set to 1, memory bits are assigned to common pins in ascending order. When the LCD32BDSP.COMREV bit is set to 0, memory bits are assigned to common pins in descending order. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 20-17 (Rev. 1.1)
Page 304 COM7 COM25 COM6 COM26 COM5 COM27 COM4 COM28 COM3 COM29 COM2 COM30 COM1 COM31 COM0 LCD32BDSP. · · · SEGREV bit = 1 LCD32BDSP. · · · SEGREV bit = 0 Seiko Epson Corporation 20-18 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 305 COM3 COM29 COM2 COM30 COM1 COM31 COM0 LCD32BDSP. · · · SEGREV bit = 1 LCD32BDSP. · · · SEGREV bit = 0 Figure 20.6.3.1 Display Data RAM Map (1/32 duty) Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 20-19 (Rev. 1.1)
Page 306 COM5 COM19 COM4 COM20 COM3 COM21 COM2 COM22 COM1 COM23 COM0 Unused area (general-purpose RAM) LCD32BDSP. · · · SEGREV bit = 1 LCD32BDSP. · · · SEGREV bit = 0 Seiko Epson Corporation 20-20 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 307 COM1 COM23 COM0 Unused area (general-purpose RAM) LCD32BDSP. · · · SEGREV bit = 1 LCD32BDSP. · · · SEGREV bit = 0 Figure 20.6.3.2 Display Data RAM Map (1/24 duty) Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 20-21 (Rev. 1.1)
Page 308 COM5 COM11 COM4 COM12 COM3 COM13 COM2 COM14 COM1 COM15 COM0 Unused area (general-purpose RAM) LCD32BDSP. · · · SEGREV bit = 1 LCD32BDSP. · · · SEGREV bit = 0 Seiko Epson Corporation 20-22 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 309 COM1 COM15 COM0 Unused area (general-purpose RAM) LCD32BDSP. · · · SEGREV bit = 1 LCD32BDSP. · · · SEGREV bit = 0 Figure 20.6.3.3 Display Data RAM Map (1/16 duty) Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 20-23 (Rev. 1.1)
Page 310 = 1 bit = 0 Display area 0 COM0 COM0 Unused area (general-purpose RAM) LCD32BDSP. · · · SEGREV bit = 1 LCD32BDSP. · · · SEGREV bit = 0 Seiko Epson Corporation 20-24 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 311 Display area 1 COM0 COM0 Unused area (general-purpose RAM) LCD32BDSP. · · · SEGREV bit = 1 LCD32BDSP. · · · SEGREV bit = 0 Figure 20.6.3.4 Display Data RAM Map (static drive) Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 20-25 (Rev. 1.1)
Page 312: Interrupt
Bit 7 Reserved Bits 6–4 CLKDIV[2:0] These bits select the division ratio of the LCD32B operating clock. Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the clock source of the LCD32B. Seiko Epson Corporation 20-26 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 313: Lcd32B Control Register
12–8 FRMCNT[4:0] 0x01 7–5 – – 4–0 LDUTY[4:0] 0x1f Bits 15–13 Reserved Bits 12–8 FRMCNT[4:0] These bits set the frame frequency. For more information, refer to “Frame Frequency.” Bits 7–5 Reserved Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 20-27 (Rev. 1.1)
Page 314: Lcd32B Timing Control Register 2
0 (R/W): Internal generation mode Bits 14–12 Reserved Bits 11–8 LC[3:0] These bits set the LCD panel contrast. Table 20.8.3 LCD Contrast Adjustment LCD32BPWR.LC[3:0] bits Contrast High (dark) ↑ ↓ Low (light) Bits 7–5 Reserved Seiko Epson Corporation 20-28 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 315: Lcd32B Display Control Register
For more information, see Figures 20.6.3.1 to 20.6.3.4. Bit 4 DSPREV This bit controls black/white inversion on the LCD display. 1 (R/W): Normal display 0 (R/W): Inverted display Bit 3 Reserved Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 20-29 (Rev. 1.1)
Page 316: Lcd32B Com Pin Control Registers 0 And 1
COM18DEN COM17DEN COM16DEN Bits 15–0 (LCD32BCOMC0 register) Bits 15–0 (LCD32BCOMC1 register) COMxDEN These bits configure the partial drive of the COMx pins. 1 (R/W): Normal output 0 (R/W): Off waveform output Seiko Epson Corporation 20-30 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 317: Lcd32B Interrupt Flag Register
LCD32BINTE 15–8 – 0x00 – – 7–1 – 0x00 – FRMIE Bits 15–1 Reserved Bit 0 FRMIE This bit enables the frame interrupt. 1 (R/W): Enable interrupt 0 (R/W): Disable interrupt Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 20-31 (Rev. 1.1)
Page 318: F Converter (Rfc)
• Can generate reference oscillation completion, sensor (A and B) oscillation completion, measurement counter overflow error, and time base counter overflow error interrupts. Figure 21.1.1 shows the RFC configuration. Table 21.1.1 RFC Channel Configuration of S1C31W74 Item S1C31W74 Number of channels 1 channel (Ch.0)
Page 319: Input/Output Pins And External Connections
Figure 21.2.2.1 Connection Example in Resistive Sensor DC Oscillation Mode SENBn SEN1 SENAn REFn RFINn : Reference resistor : Resistive sensor (AC bias) SEN1 S1C31 RFC : Reference capacitor Figure 21.2.2.2 Connection Example in Resistive Sensor AC Oscillation Mode Seiko Epson Corporation 21-2 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 320: Clock Settings
(Clear interrupt flags) - Set the interrupt enable bits in the RFC_nINTE register to 1. (Enable interrupts) 3. Assign the RFC input/output function to the ports. (Refer to the “I/O Ports” chapter.) Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 21-3 (Rev. 1.1)
Page 321: Operating Modes
To obtain the difference between the reference oscillation and sensor oscillation clock count values from the measurement counter simply, appropriate initial values must be set to the measurement counter before starting reference oscillation. Seiko Epson Corporation 21-4 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 322: Converting Operations And Control Procedure
The measurement counter overflow sets the RFC_nINTF.EREFIF bit to 1 indicating that the reference os- cillation has been terminated normally. If the RFC_nINTE.EREFIE bit = 1, a reference oscillation comple- tion interrupt request occurs at this point. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 21-5 (Rev. 1.1)
Page 323 Performing reference oscillation and sensor oscillation with the same resistor and capacitor results n ≈ m. The difference between n and m is a conversion error. Table 21.4.4.1 lists the error factors. (n: measurement counter initial value, m: measurement counter value at the end of sensor oscillation) Seiko Epson Corporation 21-6 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 324: Cr Oscillation Frequency Monitoring Function
The RFC provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the CPU only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For more infor- mation on interrupt control, refer to the “Interrupt” chapter. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 21-7 (Rev. 1.1)
Page 325: Control Registers
This bit sets the RFCLKOn pin to output the divided-by-two oscillation clock. 1 (R/W): Divided-by-two clock output 0 (R/W): Oscillation clock output For more information, refer to “CR Oscillation Frequency Monitoring Function.” Seiko Epson Corporation 21-8 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 326: Rfc Ch.n Oscillation Trigger Register
This bit controls CR oscillation for sensor A. This bit also indicates the CR oscillation status. 1 (W): Start oscillation 0 (W): Stop oscillation 1 (R): Being oscillated 0 (R): Stopped Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 21-9 (Rev. 1.1)
Page 327: Rfc Ch.n Measurement Counter Low And High Registers
Note: The time base counter must be set from the low-order value (RFC_nTCL.TC[15:0] bits) first when data is set using a 16-bit access instruction. The counter may not be set to the correct value if the high-order value (RFC_nTCH.TC[23:16] bits) is written first. Seiko Epson Corporation 21-10 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 328: Rfc Ch.n Interrupt Flag Register
RFC_nINTE.OVTCIE bit: Time base counter overflow error interrupt RFC_nINTE.OVMCIE bit: Measurement counter overflow error interrupt RFC_nINTE.ESENBIE bit: Sensor B oscillation completion interrupt RFC_nINTE.ESENAIE bit: Sensor A oscillation completion interrupt RFC_nINTE.EREFIE bit: Reference oscillation completion interrupt Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 21-11 (Rev. 1.1)
Page 329: Usb 2.0 Fs Device Controller (Usb, Usbmisc)
• Incorporates total 256-byte FIFO for endpoints (64 bytes for each endpoint). • 48 MHz clock or PLL clock (12 MHz × 4) input Figure 22.1.1 shows the USB controller configuration. Table 22.1.1 USB Controller Configuration of S1C31W74 Item S1C31W74...
Page 330: Input/Output Pins And External Connections
Figure 22.2.2.1 shows a connection diagram between the USB controller pins of this IC and an external USB de- vice. The USB_DP pin has a built-in pull up resistor that can be enabled/disabled via software. Seiko Epson Corporation 22-2 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 331: Clock Settings
Clocks” chapter. For the clock source control timings, refer to Section 22.5.1, “Initialization.” Clock supply during debugging In debug state, control the USB clock in the same way as normal operation. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 22-3 (Rev. 1.1)
Page 332: Usb Power Supply
USB and logic core connected to the USB circuit to enable the USB block connections. Start USB register settings Figure 22.5.1.1 Processing flow before and after V is connected (when PLL is used) Seiko Epson Corporation 22-4 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 333 5. Configure the VBUS_MON port as the SVD external input (refer to the “I/O Ports” chapter). 6. Activate the SVD for detecting V disconnection (refer to the “Supply Voltage Detector” chapter). Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 22-5 (Rev. 1.1)
Page 334: Settings When Vbus Is Disconnected
8. Set the USBCTL.AUTONEGOEN bit to 1. (Enable auto-negotiation) 22.5.2 Settings when V is Disconnected Use the SVD for detecting V disconnection (Detach) and perform the processing shown below when a detection interrupt has occurred. Seiko Epson Corporation 22-6 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 335: Transaction Control
1. The host issues a SETUP token addressed to EP0 of this node. 2. Next, the host sends an 8-byte data packet. 3. The USB controller writes this data to the USBEP0SETUP0 to 7 registers. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 22-7 (Rev. 1.1)
Page 336 5a. The USB controller does not update the FIFO. 6a. The USB controller does not set the USBEPnINTF.OUTACKIF bit. 7a. The USB controller does not set the USBEPmINTF.OUTSHACKIF and USBEPmCTL.FNAK bits. Seiko Epson Corporation 22-8 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 337: Control Transfer
Control transfer on EP0 consists of a setup stage, a data stage, and a status stage that are controlled as a combina- tion of a number of discrete transactions. A control transfer sequence for an OUT data stage is shown below. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 22-9 (Rev. 1.1)
Page 338 If the FIFO has an available space, the USB controller automatically receives data. For more information, refer to “OUT transfer” in Section 22.5.6, “Data Flow Control.” Furthermore, monitor the USBEP0INTF.INNAKIF bit (an interrupt can be used) and transit to the status stage if it is set. Seiko Epson Corporation 22-10 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 339: Bulk Transfer/Interrupt Transfer
Bulk and interrupt transfers at a general-purpose endpoint EPm, can be controlled either as a data flow (refer to Section 22.5.6, “Data Flow Control”) or as a series of discrete transactions (refer to Section 22.5.3, “Transaction Control”). Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 22-11 (Rev. 1.1)
Page 340: Data Flow Control
Figure 22.5.6.2 shows a data flow in IN transfer. In this example, the FIFO area assigned to this endpoint is as- sumed to be twice as large as the maximum packet size. Seiko Epson Corporation 22-12 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 341: Auto-Negotiation Function
Detach processing, therefore, this function should be enabled after Attach has detected and disabled after Detach is detected. Check each interrupt flag (USBSIEINTF.RESETIF bit and USBSIEINTF.SUSPENDIF bit) to confirm what has been actually detected. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 22-13 (Rev. 1.1)
Page 342 USBSIEINTF.RESETIF bit or the USBSIEINTF.SUSPENDIF bit is set and a Reset detection or Suspend detection interrupt is generated. If the state is determined to be Suspend, the USB controller enters IN_SUSPEND state. Seiko Epson Corporation 22-14 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 343: Description By Negotiation Function
J state Last activity USB_DP/USB_DM pins J state Internal USB clock Fully meet USB 2.0 required frequency * The SNOOZE signal should be controlled using the USBMISCCTL.USBSNZ bit. Figure 22.5.8.1 Suspend Timing Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 22-15 (Rev. 1.1)
Page 344 The description above assumes that the oscillator circuit is operating (the 48-MHz clock is supplied to the USB controller, and the CPU is not in SLEEP mode). If the CPU is in SLEEP mode and the oscillator is deactivated, an oscillation stabilization waiting time is required before resuming. Seiko Epson Corporation 22-16 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 345 "00" (Normal operation mode) USBSTAT.LINESTAT[1:0] J state USB_DP/USB_DM pins FS Idle (J state) Internal USB clock Fully meet USB 2.0 required frequency Clock stabilization waiting time Figure 22.5.8.3 Device Attach Timing Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 22-17 (Rev. 1.1)
Page 346: Fifo Management
Therefore, unless the descriptor area has been changed, there is no need to re-set the infor- mation recorded within the area since it will never be cleared otherwise. Seiko Epson Corporation 22-18 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 347 The transfer source/destination and control data must be set for the DMA controller and the relevant DMA channel must be enabled to start a DMA transfer in advance. For more information on DMA, refer to the “DMA Controller” chapter. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 22-19 (Rev. 1.1)
Page 348: Snooze
Notes: • Be sure to avoid accessing to the USB controller for five 48-MHz clock cycles from the SNOOZE signal being asserted/negated. • Be sure to avoid accessing to the FIFO while the 48 MHz clock is stopped after the SNOOZE signal is asserted. Seiko Epson Corporation 22-20 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 349: Interrupts
* These interrupt flags are provided to easily determine the cause of the interrupt generated; they indicate that an interrupt flag in an interrupt group of which interrupt has been enabled is set. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 22-21 (Rev. 1.1)
Page 350: Dma Transfer Requests
Note: Do not perform 32-bit access to read and write from/to the USB registers as it may cause mal- function. USB Control Register Register name Bit name Initial Reset Remarks USBCTL BUSDETDIS H0/S0 – AUTONEGOEN H0/S0 NONJDETEN H0/S0 JDETEN H0/S0 WAKEUP H0/S0 2–1 – – USBEN H0/S0 Seiko Epson Corporation 22-22 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 351 Since this bit is cleared to 0 after an initial reset, all USB functions are stopped. The operation as a USB device will be enabled by setting this bit to 1 after the configuration of this USB controller has completed. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 22-23 (Rev. 1.1)
Page 352: Usb Transceiver Control Register
Note: This bit is fixed at 1, as this IC supports FS mode only. Bits 5–2 Reserved Bits 1–0 LINESTAT[1:0] These bits indicate the USB bus status (signal status at the USB_DP and USB_DM pins). Seiko Epson Corporation 22-24 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 353: Usb Endpoint Control Register
USBGPEPFIFOCLR 7–3 – 0x00 – – EPCFIFOCLR H0/S0 EPBFIFOCLR H0/S0 EPAFIFOCLR H0/S0 Bits 7–3 Reserved Bit 2 EPCFIFOCLR This bit clears the EPc FIFO. 1 (R/W): Clear EPc FIFO 0 (R/W): Ineffective Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 22-25 (Rev. 1.1)
Page 354: Usb Fifo Read Cycle Setup Register
– USBEP0SETUP7 7–0 WLEN[15:8] 0x00 – – Eight-byte data received at EP0 SETUP stage are stored from the USBEP0SETUP0 register sequentially. The con- tents stored in each register are listed below. Seiko Epson Corporation 22-26 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 355: Usb Address Register
USB EP0 Maximum Packet Size Register Register name Bit name Initial Reset Remarks USBEP0SIZE – – – 6–3 MAXSIZE[3:0] H0/S0 2–0 – Bit 7 Reserved Bits 6–3 MAXSIZE[3:0] These bits set the EP0 maximum packet size. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 22-27 (Rev. 1.1)
Page 356: Usb Ep0 In Transaction Control Register
This bit clears the toggle sequence bit in the IN transaction of EP0, to 0. 1 (W): Clear toggle sequence bit 0 (W): Ineffective 0 (R): Always 0 when being read Seiko Epson Corporation 22-28 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 357: Usb Ep0 Out Transaction Control Register
This bit clears the toggle sequence bit in the OUT transaction of EP0, to 0. 1 (W): Clear toggle sequence bit 0 (W): Ineffective 0 (R): Always 0 when being read Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 22-29 (Rev. 1.1)
Page 358: Usb Epm Control Registers
USBEPmCTL.SPKTEN bit is set to 1, that data may be included in transmission. Therefore, do not write data into the FIFO until the packet transmission completes and this bit is cleared. Seiko Epson Corporation 22-30 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 359: Usb Epm Configuration Registers
Initial Reset Remarks USBEPmCFG H0/S0 – TGLMOD H0/S0 EPEN H0/S0 – – 3–0 EPNUM[3:0] H0/S0 Bit 7 This bit sets the transfer direction of EPm. 1 (R/W): IN 0 (R/W): OUT Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 22-31 (Rev. 1.1)
Page 360: Usb Epm Maximum Packet Size Registers
EPBRD Bit 0 EPARD These bits specify the endpoint from which FIFO data is read. 1 (R/W): Enable reading data from EPm FIFO 0 (R/W): Disable reading data from EPm FIFO Seiko Epson Corporation 22-32 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 361: Usb Write Fifo Select Register
1 (R/W): Enable USBWRFIFOSEL register 0 (R/W): Disable USBWRFIFOSEL register When this bit is set to 1, the CPU can write data to the FIFO of the endpoint selected by the USB- WRFIFOSEL register. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 22-33 (Rev. 1.1)
Page 362: Usb Remaining Fifo Data Count Register
USBEPmINTF register. 5–2 – – – EP0IF H0/S0 Cleared by writing 1 to the interrupt flag in the USBEP0INTF register. EP0SETIF H0/S0 Cleared by writing 1. Bits 5–2 Reserved Seiko Epson Corporation 22-34 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 363: Usb Sie Interrupt Flag Register
Bit 0 ATADDRIF These bits indicate the SIE interrupt cause occurrence status. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 22-35 (Rev. 1.1)
Page 364: Usb General-Purpose Endpoint Interrupt Flag Register
Register name Bit name Initial Reset Remarks USBEP0INTF 7–6 – – – INACKIF H0/S0 Cleared by writing 1. OUTACKIF H0/S0 INNAKIF H0/S0 OUTNAKIF H0/S0 INERRIF H0/S0 OUTERRIF H0/S0 Bits 7–6 Reserved Seiko Epson Corporation 22-36 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 365 Bit 0 OUTERRIF These bits indicate the EPm interrupt cause occurrence status. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 22-37 (Rev. 1.1)
Page 366: Usb Main Interrupt Enable Register
USB SIE Interrupt Enable Register Register name Bit name Initial Reset Remarks USBSIEINTE (reserved) H0/S0 – NONJIE H0/S0 RESETIE H0/S0 SUSPENDIE H0/S0 SOFIE H0/S0 H0/S0 – – ATADDRIE H0/S0 Bit 7 Reserved Bit 1 Reserved Seiko Epson Corporation 22-38 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 367: Usb General-Purpose Endpoint Interrupt Enable Register
GPEPIE bit must be set to 1 in addition to this register. USB EP0 Interrupt Enable Register Register name Bit name Initial Reset Remarks USBEP0INTE 7–6 – – – INACKIE H0/S0 OUTACKIE H0/S0 INNAKIE H0/S0 OUTNAKIE H0/S0 INERRIE H0/S0 OUTERRIE H0/S0 Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 22-39 (Rev. 1.1)
Page 368: Usb Epm Interrupt Enable Registers
EPm ACK reception interrupt USBEPmINTE.OUTACKIE bit: EPm ACK transmission interrupt USBEPmINTE.INNAKIE bit: EPm NAK reception interrupt USBEPmINTE.OUTNAKIE bit: EPm NAK transmission interrupt USBEPmINTE.INERRIE bit: EPm STALL reception interrupt USBEPmINTE.OUTERRIE bit: EPm STALL transmission interrupt Seiko Epson Corporation 22-40 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 369: Usb Fifo Data Register
This bit sets the number of bus access cycles for accessing a USB register. Table 22.8.5 Number of Bus Access Cycles for Accessing USB register USBMISCCTL.USBWAIT bit Number of bus access cycles System clock frequency 21 MHz (max.) 4 MHz (max.) Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 22-41 (Rev. 1.1)
Page 370 This bit puts/releases the USB circuits into/from reset state asynchronously with the clock. 1 (R/W): Release USB circuit from reset state 0 (R/W): Put USB circuit into reset state For the control timing, refer to Section 22.5.1, “Initialization.” Bit 2 Reserved Seiko Epson Corporation 22-42 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 371: Usb Fifo Write Dma Request Enable Register
(USBREMDATCNT.REMDAT[6:0] bits ≠ 0). 1 (R/W): Enable DMA transfer request 0 (R/W): Disable DMA transfer request Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented chan- nels are ineffective. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 22-43 (Rev. 1.1)
Page 372: Electrical Characteristics
Gate capacitor for USBOSC oscillator – – GUSB Drain capacitor for USBOSC oscillator – – DUSB Debug pin pull-up resistors – – DBG1–2 Capacitor between V and V – – µF Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 23-1 (Rev. 1.1)
Page 373: Current Consumption
SYSCLK = OSC3, FLASHCWAIT.RDWAIT[1:0] bits = 0x0 (1 cycle) *1 OSC1 oscillator: CLGOSC1.INV1N[1:0] bits = 0x0, CLGOSC1.CGI1[2:0] bits = 0x0, CLGOSC1.OSDEN bit = 0, = 0 pF, Crystal resonator = C-002RX (manufactured by Seiko Epson Corporation, R = 50 kW (Max.), C = 7 pF) *2 OSC3 oscillator: CLGOSC3.OSC3MD[1:0] bits = 0x2, CLGOSC3.OSC3INV[1:0] bits = 0x0, C...
Page 374 IOSC = OFF, OSC1 = 32 kHz, OSC3 = ON (ceramic oscillator), Ta = 25 °C, CLGOSC3.OSC3INV[1:0] bits = 0x3, Typ. value 5,000 4,500 3 cycles 4,000 2 cycles 3,500 3,000 2,500 1 cycle 2,000 1,500 1,000 Ta [°C] [MHz] OSC3 Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 23-3 (Rev. 1.1)
Page 375: System Reset Controller (Src) Characteristics
= 0 V, Ta = -40 to 85 °C Item Symbol Condition Min. Typ. Max. Unit – – µs Reset hold time RSTR *1 Time until the internal reset signal is negated after the reset request is canceled. Seiko Epson Corporation 23-4 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 376 = 1.8 to 3.6 V, PWGACTL.REGSEL bit = 1, Typ. value = 1.8 to 3.6 V, PWGACTL.REGSEL bit = 0, Typ. value CLGIOSC.IOSCFQ[2:0] bits = 0x1 CLGIOSC.IOSCFQ[2:0] bits = 0x7 Ta [°C] Ta [°C] Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 23-5 (Rev. 1.1)
Page 377: Flash Memory Characteristics
CLGOSC1.OSDEN bit = 1 – 0.025 µA OSD1 *1 Crystal resonator = C-002RX (manufactured by Seiko Epson Corporation, R = 50 kW (Max.), C = 7 pF) OSC3 oscillator circuit characteristics Unless otherwise specified: V = 1.8 to 3.6 V, V = 0 V, Ta = 25 °C...
Page 378 1,038 SVD2_nCTL.SVDC[4:0] bits = 0x1a 1,053 SVD2_nCTL.SVDC[4:0] bits = 0x1b 1,086 SVD2_nCTL.SVDC[4:0] bits = 0x1c 1,094 SVD2_nCTL.SVDC[4:0] bits = 0x1d 1,102 SVD2_nCTL.SVDC[4:0] bits = 0x1e 1,130 SVD2_nCTL.SVDC[4:0] bits = 0x1f 1,147 Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 23-7 (Rev. 1.1)
Page 379 *1 If CLK_SVD2_n is configured in the neighborhood of 32 kHz, the SVD2_nINTF.SVDDT bit is masked during the t period and SVDEN it retains the previous value. CLK_SVD2_n SVD2_nCTL.MODEN 0x1e 0x10 SVD2_nCTL.SVDC[4:0] SVD2_nINTF.SVDDT Invalid Valid Invalid Valid SVDEN Seiko Epson Corporation 23-8 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 380: Uart (Uart2) Characteristics
SDOn output delay time = 15 pF 3.0 to 3.6 V mode0 – – 1.8 to 3.0 V mode0 – – 1.8 to 3.6 V mode1 – – *1 C = Pin load Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 23-9 (Rev. 1.1)
Page 381 (CPOL, CPHA) = (1, 0) or (0, 1) SPICLKn (CPOL, CPHA) = (1, 1) or (0, 0) SDIn SDOn Slave mode #SPISSn SPICLKn (CPOL, CPHA) = (0, 1) SPICLKn (CPOL, CPHA) = (1, 0) SDIn Hi-Z SDOn Seiko Epson Corporation 23-10 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 382 QSDIOn[3:0] output stop time = 15 pF 3.0 to 3.6 V mode0 – – 1.8 to 3.0 V mode0 – – 1.8 to 3.6 V mode1 – – *1 C = Pin load Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 23-11 (Rev. 1.1)
Page 383: C (I2C) Characteristics
5.22 5.49 5.76 LCD32BPWR.LC[3:0] bits = 0xc 5.28 5.56 5.84 LCD32BPWR.LC[3:0] bits = 0xd 5.36 5.64 5.92 LCD32BPWR.LC[3:0] bits = 0xe 5.43 5.72 6.01 LCD32BPWR.LC[3:0] bits = 0xf 5.51 5.80 6.09 Seiko Epson Corporation 23-12 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 384 *1 Other LCD driver settings: LCD32BPWR.LC[3:0] bits = 0xf, CLK_LCD32B = 32 kHz, LCD32BTIM1.FRMCNT[4:0] bits = 0x01 (frame frequency = 64 Hz) *2 The value is added to the current consumption in HALT/RUN mode. Current consumption increases according to the display contents and panel load. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 23-13 (Rev. 1.1)
Page 385 Ta = 25 °C, Typ. value, LCD32BPWR.LC[3:0] bits = 0xf, when a load is connected to the V pin only when a load is connected to the V pin only [µA] [µA] Seiko Epson Corporation 23-14 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 386 = 100 kW, Ta = 25 °C, Typ. value 1,000 1,000 3.6 V 3.6 V 1.8 V 1.8 V ∆f /∆IC ∆f /∆IC RFCLK RFCLK 1,000 10,000 1,000 10,000 100,000 [kΩ] [pF] Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 23-15 (Rev. 1.1)
Page 387: Usb 2.0 Fs Device Controller (Usb) Characteristics
Ta = 25 °C *1 Current flowing through the V pin in HID device class (1 transfer per ms) USB circuit curent-V voltage characteristic USBMISCCTL.USBCLKSEL bit = 0, Ta = 25 °C, Typ. value Seiko Epson Corporation 23-16 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 388: Basic External Connection Diagram
*1: For Flash programming *2: When the LCD driver is used *3: When 1/4 bias is selected *4: When 1/5 bias is selected ( ): Do not mount components if unnecessary. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 24-1 (Rev. 1.1)
Page 389 Symbol Name Recommended components X'tal1 32 kHz crystal resonator C-002RX (R = 50 kW (Max.), C = 7 pF) manufactured by Seiko Epson Corporation OSC1 gate capacitor Trimmer capacitor or ceramic capacitor OSC1 drain capacitor Ceramic capacitor X’tal3 Crystal resonator...
Page 390: Package
– 0.26 – 0.36 – – 0.08 – – 0.10 0.15 0.25 0.35 0.15 0.25 0.35 A1 Corner 1 2 3 4 5 6 9 1011121314 Figure 25.1 VFBGA8H-181 Package Dimensions Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL 25-1 (Rev. 1.1)
Page 391: System Register (Sys)
– – – 0046 (CLG OSC1 Control OSDRB R/WP Register) OSDEN R/WP OSC1BUP R/WP – – 10–8 CGI1[2:0] R/WP 7–6 INV1B[1:0] R/WP 5–4 INV1N[1:0] R/WP 3–2 – – 1–0 OSC1WT[1:0] R/WP Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL AP-A-1 (Rev. 1.1)
Page 392: 0X4000 0080
STATNMI 7–5 – – WDTCNTRST Always read as 0. 3–0 WDTRUN[3:0] R/WP – 0x4000 WDT2CMP 15–10 – 0x00 – – 00a4 (WDT2 Counter Com- 9–0 CMP[9:0] 0x3ff R/WP pare Match Register) Seiko Epson Corporation AP-A-2 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 393: 0X4000 00C0-0X4000 00D2
00cc (RTCA Month/Day RTCMOH Register) 11–8 RTCMOL[3:0] 7–6 – – 5–4 RTCDH[1:0] 3–0 RTCDL[3:0] 0x4000 RTCAYAR 15–11 – 0x00 – – 00ce (RTCA Year/Week 10–8 RTCWK[2:0] Register) 7–4 RTCYH[3:0] 3–0 RTCYL[3:0] Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL AP-A-3 (Rev. 1.1)
Page 394: 0X4000 0100-0X4000 0106
Interrupt Flag 7–1 – 0x00 – Register) SVDIF Cleared by writing 1. 0x4000 SVD2_0INTE 15–8 – 0x00 – – 0106 (SVD2 Ch.0 Interrupt 7–1 – 0x00 – Enable Register) SVDIE Seiko Epson Corporation AP-A-4 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 395: 0X4000 0160-0X4000 016C
15–8 – 0x00 – – 020a (P0 Port Chattering Filter Enable 7–0 P0CHATEN[7:0] 0x00 Register) 0x4000 PPORTP0MODSEL 15–8 – 0x00 – – 020c (P0 Port Mode Select 7–0 P0SEL[7:0] 0x00 Register) Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL AP-A-5 (Rev. 1.1)
Page 396 15–8 – 0x00 – – 022a (P2 Port Chattering Filter Enable 7–0 P2CHATEN[7:0] 0x00 Register) 0x4000 PPORTP2MODSEL 15–8 – 0x00 – – 022c (P2 Port Mode Select 7–0 P2SEL[7:0] 0x00 Register) Seiko Epson Corporation AP-A-6 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 397 15–8 – 0x00 – – 024a (P4 Port Chattering Filter Enable 7–0 P4CHATEN[7:0] 0x00 Register) 0x4000 PPORTP4MODSEL 15–8 – 0x00 – – 024c (P4 Port Mode Select 7–0 P4SEL[7:0] 0x00 Register) Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL AP-A-7 (Rev. 1.1)
Page 398 15–8 – 0x00 – – 026a (P6 Port Chattering Filter Enable 7–0 P6CHATEN[7:0] 0x00 Register) 0x4000 PPORTP6MODSEL 15–8 – 0x00 – – 026c (P6 Port Mode Select 7–0 P6SEL[7:0] 0x00 Register) Seiko Epson Corporation AP-A-8 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 399 (P8 Port Interrupt 9–8 P8EDGE[1:0] Control Register) 7–2 – 0x00 – 1–0 P8IE[1:0] 0x4000 PPORTP8CHATEN 15–8 – 0x00 – – 028a (P8 Port Chattering 7–2 – 0x00 – Filter Enable Register) 1–0 P8CHATEN[1:0] Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL AP-A-9 (Rev. 1.1)
Page 400 (Pd Port Mode Select 7–4 – – Register) 3–0 PDSEL[3:0] 0x4000 PPORTPDFNCSEL 15–8 – 0x00 – – 02de (Pd Port Function 7–6 PD3MUX[1:0] Select Register) 5–4 PD2MUX[1:0] 3–2 PD1MUX[1:0] 1–0 PD0MUX[1:0] Seiko Epson Corporation AP-A-10 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 401: 0X4000 0300-0X4000 031E
10–8 P11PERISEL[2:0] Setting Register) 7–5 P10PPFNC[2:0] 4–3 P10PERICH[1:0] 2–0 P10PERISEL[2:0] 0x4000 UPMUXP1MUX1 15–13 P13PPFNC[2:0] – 030a (P12–13 Universal 12–11 P13PERICH[1:0] Port Multiplexer 10–8 P13PERISEL[2:0] Setting Register) 7–5 P12PPFNC[2:0] 4–3 P12PERICH[1:0] 2–0 P12PERISEL[2:0] Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL AP-A-11 (Rev. 1.1)
Page 402: 0X4000 0380-0X4000 0392
5–4 CLKDIV[1:0] 3–2 – – 1–0 CLKSRC[1:0] 0x4000 UART2_0MOD 15–11 – 0x00 – – 0382 (UART2 Ch.0 Mode BRDIV Register) INVRX INVTX – – PUEN OUTMD IRMD CHLN PREN PRMD STPB Seiko Epson Corporation AP-A-12 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 403: 0X4000 03A0-0X4000 03Ac
03a0 (T16 Ch.1 Clock DBRUN Control Register) 7–4 CLKDIV[3:0] 3–2 – – 1–0 CLKSRC[1:0] 0x4000 T16_1MOD 15–8 – 0x00 – – 03a2 (T16 Ch.1 Mode 7–1 – 0x00 – Register) TRMD Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL AP-A-13 (Rev. 1.1)
Page 404: 0X4000 03B0-0X4000 03Be
7–4 – – Enable Register) OEIE TENDIE RBFIE TBEIE 0x4000 SPIA_0TBEDMAEN 15–8 – 0x00 – – 03bc (SPIA Ch.0 Transmit 7–4 – – Buffer Empty DMA Request Enable 3–0 TBEDMAEN[3:0] Register) Seiko Epson Corporation AP-A-14 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 405: 0X4000 03C0-0X4000 03D6
Cleared by writing 1. GCIF H0/S0 NACKIF H0/S0 STOPIF H0/S0 STARTIF H0/S0 ERRIF H0/S0 RBFIF H0/S0 Cleared by reading the I2C_0RXD register. TBEIF H0/S0 Cleared by writing to the I2C_0TXD register. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL AP-A-15 (Rev. 1.1)
Page 406: 0X4000 0400-0X4000 041C
Status Register) CAPI1 CAPI0 UP_DOWN 0x4000 T16B_0INTF 15–8 – 0x00 – – 040a (T16B Ch.0 Interrupt 7–6 – – Flag Register) CAPOW1IF Cleared by writing 1. CMPCAP1IF CAPOW0IF CMPCAP0IF CNTMAXIF CNTZEROIF Seiko Epson Corporation AP-A-16 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 407: 0X4000 0440-0X4000 045C
16-bit PWM Timer (T16B) Ch.1 Address Register name Bit name Initial Reset Remarks 0x4000 T16B_1CLK 15–9 – 0x00 – – 0440 (T16B Ch.1 Clock DBRUN Control Register) 7–4 CLKDIV[3:0] – – 2–0 CLKSRC[2:0] Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL AP-A-17 (Rev. 1.1)
Page 408 – 0452 (T16B Ch.1 Compare/ Capture 0 Data Register) 0x4000 T16B_1CC0DMAEN 15–8 – 0x00 – – 0454 (T16B Ch.1 Compare/ 7–4 – – Capture 0 DMA Request Enable 3–0 CC0DMAEN[3:0] Register) Seiko Epson Corporation AP-A-18 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 409: 0X4000 0480-0X4000 048C
Register name Bit name Initial Reset Remarks 0x4000 UART2_1CLK 15–9 – 0x00 – – 0600 (UART2 Ch.1 Clock DBRUN Control Register) 7–6 – – 5–4 CLKDIV[1:0] 3–2 – – 1–0 CLKSRC[1:0] Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL AP-A-19 (Rev. 1.1)
Page 410 3–0 TBEDMAEN[3:0] Empty DMA Request Enable Register) 0x4000 UART2_1 15–8 – 0x00 – – 0612 RB1FDMAEN (UART2 Ch.1 Receive 7–4 – – Buffer One Byte Full 3–0 RB1FDMAEN[3:0] DMA Request Enable Register) Seiko Epson Corporation AP-A-20 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 411: 0X4000 0680-0X4000 068C
7–4 – – Register) MSTSSO SFTRST MODEN 0x4000 QSPI_0TXD 15–0 TXD[15:0] 0x0000 – 0694 (QSPI Ch.0 Transmit Data Register) 0x4000 QSPI_0RXD 15–0 RXD[15:0] 0x0000 – 0696 (QSPI Ch.0 Receive Data Register) Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL AP-A-21 (Rev. 1.1)
Page 412: 0X4000 06C0-0X4000 06D6
Register name Bit name Initial Reset Remarks 0x4000 I2C_1CLK 15–9 – 0x00 – – 06c0 (I2C Ch.1 Clock DBRUN Control Register) 7–6 – – 5–4 CLKDIV[1:0] 3–2 – – 1–0 CLKSRC[1:0] Seiko Epson Corporation AP-A-22 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 413 – Buffer Empty DMA Request Enable 3–0 TBEDMAEN[3:0] Register) 0x4000 I2C_1RBFDMAEN 15–8 – 0x00 – – 06d6 (I2C Ch.1 Receive 7–4 – – Buffer Full DMA Request Enable 3–0 RBFDMAEN[3:0] Register) Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL AP-A-23 (Rev. 1.1)
Page 414: 0X4000 0700-0X4000 070C
Register) bit. 7–5 – – – REMOINV BUFEN TRMD REMCRST MODEN 0x4000 REMC2DBCNT 15–0 DBCNT[15:0] 0x0000 H0/S0 Cleared by writing 1 to the 0724 REMC2DBCTL.REMCRST (REMC2 Data Bit bit. Counter Register) Seiko Epson Corporation AP-A-24 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 415: 0X4000 0800-0X4000 0812
Control Register 2) 7–5 – – 4–0 NLINE[4:0] 0x00 0x4000 LCD32BPWR EXVCSEL – 0808 (LCD32B Power 14–12 – – Control Register) 11–8 LC[3:0] 7–5 – – BSTEN BIASSEL HVLD – – VCEN Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL AP-A-25 (Rev. 1.1)
Page 416: 0X4000 0840-0X4000 0850
Register name Bit name Initial Reset Remarks 0x4000 RFC_0CLK 15–9 – 0x00 – – 0840 (RFC Ch.0 Clock DBRUN Control Register) 7–6 – – 5–4 CLKDIV[1:0] 3–2 – – 1–0 CLKSRC[1:0] Seiko Epson Corporation AP-A-26 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 417: 0X2040 0000-0X2040 0104, 0X4000 0970-0X4000 0976
H0/S0 – 0003 (USB Transceiver 6–2 – 0x00 – Control Register) 1–0 OPMOD[1:0] H0/S0 0x2040 USBSTAT VBUSSTAT – – 0004 (USB Status Register) FSMOD – 5–2 – – 1–0 LINESTAT[1:0] – Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL AP-A-27 (Rev. 1.1)
Page 418 – 0x2040 USBEP0ICTL – – – 001c (USB EP0 IN SPKTEN H0/S0 Transaction Control – – Register) TGLSTAT H0/S0 TGLSET H0/S0 Read as 0. TGLCLR H0/S0 FNAK H0/S0 – FSTALL H0/S0 Seiko Epson Corporation AP-A-28 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 419 – 0035 (USB EPc Maximum 6–0 MAXSIZE[6:0] 0x00 H0/S0 Packet Size Register) 0x2040 USBRDFIFOSEL 7–3 – 0x00 – – 0040 (USB Read FIFO EPCRD H0/S0 Select Register) EPBRD H0/S0 EPARD H0/S0 Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL AP-A-29 (Rev. 1.1)
Page 420 OUTERRIF H0/S0 0x2040 USBEPAINTF – – – 0054 (USB EPa Interrupt OUTSHACKIF H0/S0 Cleared by writing 1. Flag Register) INACKIF H0/S0 OUTACKIF H0/S0 INNAKIF H0/S0 OUTNAKIF H0/S0 INERRIF H0/S0 OUTERRIF H0/S0 Seiko Epson Corporation AP-A-30 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 421 OUTNAKIE H0/S0 INERRIE H0/S0 OUTERRIE H0/S0 0x2040 USBEPBINTE – – – 0065 (USB EPb Interrupt OUTSHACKIE H0/S0 Enable Register) INACKIE H0/S0 OUTACKIE H0/S0 INNAKIE H0/S0 OUTNAKIE H0/S0 INERRIE H0/S0 OUTERRIE H0/S0 Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL AP-A-31 (Rev. 1.1)
Page 422 SVDF – 2–1 SVDMD[1:0] MODEN 0x4000 SVD2_1INTF 15–9 – 0x00 – – 0984 (SVD2 Ch.1 Status SVDDT – and Interrupt Flag 7–1 – 0x00 – Register) SVDIF Cleared by writing 1. Seiko Epson Corporation AP-A-32 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 423: 0X4000 1000-0X4000 2014
– 3–0 ENCLR[3:0] – – 0x4000 DMACPASET 31–24 – 0x00 – – 1030 (DMAC Primary-Alter- 23–16 – 0x00 – nate Set Register) 15–8 – 0x00 – 7–4 – – 3–0 PASET[3:0] Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL AP-A-33 (Rev. 1.1)
Page 424 – ERRIESET 0x4000 DMACERRIECLR 31–24 – 0x00 – – 2014 (DMAC Error Interrupt 23–16 – 0x00 – Enable Clear Register) 15–8 – 0x00 – 7–1 – 0x00 – ERRIECLR – – Seiko Epson Corporation AP-A-34 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 425: Appendix B Power Saving
• Using a crystal resonator with lower C value decreases current consumption. However, these configurations may reduce the oscillation margin and increase the frequency error, therefore, be sure to perform matching evaluation using the actual printed circuit board. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL AP-B-1 (Rev. 1.1)
Page 426: Other Power Saving Methods
• Setting the LCD voltage regulator into heavy load protection mode (LCD32BPWR.HVLD bit = 1) increases current consumption. Heavy load protection mode should be set only when the display becomes unstable. Seiko Epson Corporation AP-B-2 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 427 Sudden power supply fluctuations due to noise will cause malfunctions. Consider the following issues. (1) Connections from the power supply to the V and V pins should be implemented via the shortest, thick- est patterns possible. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL AP-C-1 (Rev. 1.1)
Page 428 (2) Electromagnetically-induced noise from a solder iron when soldering In particular, during soldering, take care to ensure that the soldering iron GND (tip potential) has the same po- tential as the IC GND. Seiko Epson Corporation AP-C-2 S1C31W74 TECHNICAL MANUAL (Rev. 1.1)
Page 429: Appendix D Measures Against Noise
• Execute the resending process via software after executing the receive error handler with a parity check. For details of the pin functions and the function switch control, see the “I/O Ports” chapter. For the UART con- trol and details of receive errors, see the “UART” chapter. Seiko Epson Corporation S1C31W74 TECHNICAL MANUAL AP-D-1 (Rev. 1.1)
Page 430: Revision History
REVISION HISTORY Revision History Code No. Page Contents 413374500 New establishment 413374501 Whole Corrected the Cortex ® -M0+ register names. manual System control register → Cortex ® -M0+ System Control Register Cortex ® -M0+ Application Interrupt and Reset Control Register Vector table offset register →...
Page 431 REVISION HISTORY Code No. Page Contents 413374501 4-10 4.9 Control Registers FLASHC Flash Read Cycle Register Added a note to the RDWAIT[1:0] bits. Notes: ... • When the FLASHCWAIT.RDWAIT[1:0] bit setting is altered from 0x2 to 0x1, add two NOP instructions immediately after that.
Page 432 REVISION HISTORY Code No. Page Contents 413374501 15-29 15.8 Control Registers QSPI Ch.n Mode Register Deleted the following description of the CHDL[3:0] bits: This setting is required to output the XIP confirmation bit to Micron Flash memories or to output the mode byte to Spansion Flash memories.
Page 433 REVISION HISTORY Code No. Page Contents 413374501 24-1 24 Basic External Connection Diagram Modified the figure. : For Flash programming Min. = 2.7 → 2.4 V was changed to that must always be connected. The ENVPP and #RESET signals were connected to the debugging tool connector. 25-1 25 Package A JEITA name was added to the package name.
Page 434 Phone: +86-755-3299-0588 Fax: +86-755-3299-0560 Epson Europe Electronics GmbH Riesstrasse 15, 80992 Munich, Germany Epson Taiwan Technology & Trading Ltd. Phone: +49-89-14005-0 Fax: +49-89-14005-110 15F, No. 100, Songren Rd, Sinyi Dist, Taipei City 110, Taiwan Phone: +886-2-8786-6688 Epson Singapore Pte., Ltd.

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