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T16B
CLK_T16B0
EXCL00
EXCL01
Clock
generator
CLK_T16Bn
EXCLn0
EXCLn1
17.2. Input/Output Pins
Table 17.2.1 lists the T16B pins.
Pin name
EXCLnm
TOUTnm/CAPn
m
If the port is shared with the T16B pin and other functions, the T16B input/output function must be
assigned to the port before activating T16B. For more information, refer to the "I/O Ports" chapter.
17-2
Counter block Ch.0
Comparator/capture block Ch.0
CBUFMD[2:0]
Compare/Capture 0
data register CC[15:0]
CNTMD[1:0]
Compare
ONEST
buffer 0
UP_DOWN
RUN
BSY
PRESET
Comparator
circuit 0
Counter
ZERO/MAX signal
TC[15:0]
Comparator
circuit 1
MAX counter data
register MC[15:0]
Compare
buffer 1
MAXBSY
MODEN
Compare/Capture 1
data register CC[15:0]
DBRUN
CLKDIV[3:0]
CLKSRC[2:0]
CBUFMD[2:0]
Counter block Ch.n
Figure 17.1.1 T16B Configuration
Table 17.2.1 List of T16B Pins
I/O*
Initial status*
I
I (Hi-Z)
O or I
O (L)
Seiko Epson Corporation
CCMD
TOUTMT
SCS
TOUTO
CAPIS[1:0]
CAPTRG[1:0]
TOUTMD[2:0]
TOUTINV
Capture
circuit 0
CAPI0
TOUT control
circuit 0
MATCH signal
TOUT control
MATCH signal
circuit 1
CAPI1
Capture
circuit 1
TOUTMT
SCS
TOUTO
CAPIS[1:0]
TOUTMD[2:0]
CAPTRG[1:0]
TOUTINV
CCMD
DMA request
control
MZDMAENx
circuit
CCmDMAENx
Interrupt
CAPOWmIE
control
CAPOWmIF
circuit
CMPCAPmIE
CMPCAPmIF
CNTMAXIE
CNTMAXIF
CNTZEROIE
CNTZEROIF
Comparator/capture block Ch.n
Function
External clock input
TOUT signal output (in comparator mode) or capture
trigger signal input (in capture mode)
* Indicates the status when the pin is configured for T16B.
CAP00
TOUT00
TOUT01
CAP01
TOUT02/03
CAP02/03
TOUT04/05
CAP04/05
To DMA controller
To CPU core
CAPn0/1
TOUTn0/1
CAPn2/3
TOUTn2/3
CAPn4/5
TOUTn4/5
To DMA controller
To CPU core
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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