Advertisement
14.8. Control Registers
SPIA Ch.n Mode Register
Register name
Bit
SPIA_nMOD
15–12
11–8
7–6
5
4
3
2
1
0
Bits 15–12
Reserved
Bits 11–8
CHLN[3:0]
These bits set the bit length of transfer data.
Bits 7–6
Reserved
Bit 5
PUEN
This bit enables pull-up/down of the input pins.
1 (R/W): Enable pull-up/down
0 (R/W): Disable pull-up/down
For more information, refer to "Input Pin Pull-Up/Pull-Down Function."
Bit 4
NOCLKDIV
This bit selects SPICLKn in master mode. This setting is ineffective in slave mode.
1 (R/W):
0 (R/W):
For more information, refer to "SPIA Operating Clock."
Bit 3
LSBFST
This bit configures the data format (input/output permutation).
1 (R/W):
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Bit name
Initial
–
0x0
CHLN[3:0]
0x7
–
0x0
PUEN
NOCLKDIV
LSBFST
CPHA
CPOL
MST
Table 14.8.1 Data Bit Length Settings
SPIA_nMOD.CHLN[3:0] bits
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
SPICLKn frequency = CLK_SPIAn frequency
( = 16-bit timer operating clock frequency)
SPICLKn frequency = 16-bit timer output frequency / 2
LSB first
Seiko Epson Corporation
Reset
R/W
–
R
H0
R/W
–
R
0
H0
R/W
0
H0
R/W
0
H0
R/W
0
H0
R/W
0
H0
R/W
0
H0
R/W
Data bit length
16 bits
15 bits
14 bits
13 bits
12 bits
11 bits
10 bits
9 bits
8 bits
7 bits
6 bits
5 bits
4 bits
3 bits
2 bits
Setting prohibited
Remarks
–
14-15
Advertisement
