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2
S
Saddr/W
I
C bus
BSY = 1
Software bit operations
Operations by the external master
S: START condition, Sr: Repeated START condition, P: STOP condition,
A: ACK, A: NACK, Saddr/W: Slave address + W(0), Data n: 8-bit data
Figure 16.4.6.1 Example of Data Receiving Operations in Slave Mode
16.4.7. Slave Operations in 10-bit Address Mode
The I2C Ch.n functions as a slave device in 10-bit address mode when the I2C_nCTL.MST bit = 0 and
the I2C_nMOD.OADR10 bit = 1.
The following shows the address receiving operations in 10-bit address mode. Figure 16.4.7.1 shows an
operation example. See Figure 16.4.4.1 for the 10-bit address configuration.
10-bit address receiving operations
After a START condition is issued, the master sends the first address that includes the two high-order
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Clock stretching by I2C
STARTIF = 1
RXD[7:0] → Data 1
A
Data 1
A
TR = 0
RBFIF = 1
STARTIF = 1
BYTEENDIF = 1
Hardware bit operations
Operations by I2C (slave mode)
Data reception
One-byte reception?
Yes
Write 1 to the I2C_nCTL.TXNACK bit
Wait for an interrupt request
(I2C_nINTF.STARTIF = 1)
Write 1 to the I2C_nINTF.STARTIF bit
Wait for an interrupt request
(I2C_nINTF.RBFIF = 1)
Last data received next?
Yes
Write 1 to the I2C_nCTL.TXNACK bit
Read receive data from the I2C_nRXD register
Last data received?
Yes
End
Figure 16.4.6.2 Slave Mode Data Reception Flowchart
Seiko Epson Corporation
RXD[7:0]→Data (N -1) RXD[7:0] → Data N
Data 2
A
Data N
RBFIF = 1
RBFIF = 1
BYTEENDIF = 1
BYTEENDIF = 1
TXNACK = 1
RXD[7:0] Data (N -1) RXD[7:0] → Data N
A
Data N
RBFIF = 1
RBFIF = 1
BYTEENDIF = 1
BYTEENDIF = 1
No
No
No
A
P
BSY = 0
STOPIF = 1
Sr
A
P
BSY = 0
TXNACK = 0
STOPIF = 1
Sr
TXNACK = 0
16-15
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