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18.3.3. Clock Supply During Debugging
The CLK_REMC3 supply during debugging should be controlled using the REMC3CLK.DBRUN bit.
The CLK_REMC3 supply to the REMC3 is suspended when the CPU enters debug state if the
REMC3CLK.DB- RUN bit = 0. After the CPU returns to normal operation, the CLK_REMC3 supply resumes.
Although the REMC3 stops operating when the CLK_REMC3 supply is suspended, the output pin and
registers retain the status before debug state was entered. If the REMC3CLK.DBRUN bit = 1, the
CLK_REMC3 supply is not suspended and the REMC3 will keep operating in debug state.
18.4. Operations
18.4.1. Initialization
The REMC3 should be initialized with the procedure shown below.
1. Write 1 to the REMC3DBCTL.REMCRST bit.
2. Configure the REMC3CLK.CLKSRC[1:0] and REMC3CLK.CLKDIV[3:0] bits. (Configure operating clock)
3. Assign the REMC3 output function to the port. (Refer to the "I/O Ports" chapter.)
4. Configure the following REMC3DBCTL register bits:
Set the REMC3DBCTL.MODEN bit to 1.
-
REMC3DBCTL.TRMD bit
-
Set the REMC3DBCTL.BUFEN bit to 1.
-
REMC3DBCTL.REMOINV bit
-
5. Configure the following REMC3CARR register bits:
REMC3CARR.CRPER[7:0] bit
-
REMC3CARR.CRDTY[7:0] bit
-
6. Configure the following REMC3CCTL register bits:
REMC3CCTL.CARREN bit
-
REMC3CCTL.OUTINVEN bit
-
7. Set the following bits when using the interrupt:
Write 1 to the interrupt flags in the REMC3INTF register.
-
Set the interrupt enable bits in the REMC3INTE register to 1.
-
18.4.2. Data Transmission Procedures
Starting data transmission
The following shows a procedure to start data transmission.
1. Set the REMC3APLEN.APLEN[15:0] bits.
2. Set the REMC3DBLEN.DBLEN[15:0] bits.
3. Set the following REMC3DBCTL register bits:
Set the REMC3DBCTL.PRESET bit to 1.
-
Set the REMC3DBCTL.PRUN bit to 1.
-
Continuous data transmission control
The following shows a procedure to send data continuously after starting data transmission (after Step 3
above).
1. Set the duty and cycle for the subsequent data to the REMC3APLEN.APLEN[15:0] and REMC3DBLEN.
DBLEN[15:0] bits, respectively, before a compare DB interrupt (REMC3INTF.DBIF bit = 1) occurs. (It is
not necessary to rewrite settings when sending the same data with the current settings.)
2. Wait for a compare DB interrupt
3. Repeat Steps 1 and 2 until the end of data.
Terminating data transmission
The following shows a procedure to terminate data transmission.
1. Wait for a compare DB interrupt
2. Set the REMC3DBCTL.PRUN bit to 0.
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
(Enable count operation clock)
(Select repeat mode/one-shot mode)
(Enable compare buffer)
(Configure inverse logic output signal)
(Set carrier signal cycle)
(Set carrier signal duty)
(Enable/disable carrier modulation)
(Configure output signal polarity)
(Set data signal duty)
(Set data signal cycle)
(Reset internal counters)
(Start counting)
(REMC3INTF.DBIF bit = 1).
(REMC3INTF.DBIF bit = 1).
(Stop counting)
Seiko Epson Corporation
(Reset REMC3)
(Clear interrupt flags)
(Enable interrupts)
18-3
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