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T16 Ch.n Reload Data Register
Register name
Bit
T16_nTR
15–0
Bits 15–0
TR[15:0]
These bits are used to set the initial value to be preset to the counter.
The value set to this register will be preset to the counter when 1 is written to the
T16_nCTL.PRESET bit or when the counter underflows.
Notes:
•
The T16_nTR register cannot be altered while the timer is running (T16_nCTL.PRUN bit
= 1), as an incorrect initial value may be preset to the counter.
•
When one-shot mode is set, the T16_nTR.TR[15:0] bits should be set to a value equal
to or greater than 0x0001.
T16 Ch.n Counter Data Register
Register name
Bit
T16_nTC
15–0
Bits 15–0
TC[15:0]
The current counter value can be read out from these bits.
T16 Ch.n Interrupt Flag Register
Register name
Bit
T16_nINTF
15–8
7–1
0
Bits 15–1
Reserved
Bit 0
UFIF
This bit indicates the T16 Ch.n underflow interrupt cause occurrence status.
1 (R): Cause of interrupt occurred
0 (R): No cause of interrupt occurred
1 (W): Clear flag
0 (W): Ineffective
T16 Ch.n Interrupt Enable Register
Register name
Bit
T16_nINTE
15–8
7–1
0
Bits 15–1
Reserved
Bit 0
UFIE
This bit enables T16 Ch.n underflow interrupts.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
Note:
To prevent generating unnecessary interrupts, the corresponding interrupt flag should
be cleared before enabling interrupts.
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Bit name
Initial
TR[15:0]
0xffff
Bit name
Initial
TC[15:0]
0xffff
Bit name
Initial
–
0x00
–
0x00
UFIF
0
Bit name
Initial
–
0x00
–
0x00
UFIE
0
Seiko Epson Corporation
Reset
R/W
H0
R/W
Reset
R/W
H0
R
Reset
R/W
–
R
–
R
H0
R/W
Cleared by writing 1.
Reset
R/W
–
R
–
R
H0
R/W
Remarks
–
Remarks
–
Remarks
–
Remarks
–
12-7
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