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T16B Ch.n Counter Max/Zero DMA Request Enable Register
Register name
Bit
T16B_nMZDMAEN 15–0
Bits 15–0
MZDMAEN[15:0]
These bits enable T16B to issue a DMA transfer request to the corresponding DMA
controller channel (Ch.0–Ch.15) when the counter value reaches the MAX value or 0x0000.
1 (R/W):
0 (R/W):
Each bit corresponds to a DMA controller channel. The high-order bits for the
unimplemented channels are ineffective.
T16B Ch.n Compare/Capture m DMA Request Enable Register
Register name
Bit
T16B_nCCmDMAEN
15–0
Bits 15–0
CCmDMAEN[15:0]
These bits enable T16B to issue a DMA transfer request to the corresponding DMA
controller channel (Ch.0–Ch.15) when the counter value reaches the compare data or is
captured.
1 (R/W):
0 (R/W):
Each bit corresponds to a DMA controller channel. The high-order bits for the
unimplemented channels are ineffective.
17-36
Bit name
Initial
MZDMAEN[15:0]
0x0000
Enable DMA transfer request
Disable DMA transfer request
Bit name
Initial
CCmDMAEN[15:0]
0x0000
Enable DMA transfer request
Disable DMA transfer request
Seiko Epson Corporation
Reset
R/W
H0
R/W
Reset
R/W
H0
R/W
Remarks
–
Remarks
–
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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