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2.1.2. Pins
Table 2.1.2.1 lists the PWGA pins.
Pin
I/O
VDD
P
name
VSS
P
VD1
A
VDDQSPI
P
For the VDD/VDDQSPI operating voltage ranges and recommended external parts, refer to
"Recommended Operating Conditions, Power supply voltage VDD/VDDQSPI" in the "Electrical
Characteristics" chapter and the "Basic External Connection Diagram" chapter, respectively.
2.1.3. V
Regulator Operation Mode
D1
The VD1 regulator supports two operation modes, normal mode and economy mode. Setting the VD1
regulator into economy mode at light loads helps achieve low-power operations. Table 2.1.3.1 lists
examples of light load conditions in which economy mode can be set.
Table 2.1.3.1 Examples of Light Load Conditions in which Economy Mode Can be Set
SLEEP mode (when all oscillators are stopped, or OSC1 only is active)
HALT mode (when OSC1 only is active)
RUN mode (when OSC1 only is active)
The VD1 regulator also supports automatic mode in which the hardware detects a light load condition and
automatically switches between normal mode and economy mode. Use the VD1 regulator in automatic
mode when no special control is required.
2-2
Table 2.1.2.1 List of PWGA Pins
Initial status
–
Power supply (+)
–
GND
–
VD1 regulator output pin
–
Power supply (+) for SPI-Flash
Light load condition
Seiko Epson Corporation
Function
Exceptions
When a clock source except for
OSC1 is active
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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